ACT 5261
64-Bit Superscaler Microprocessor
Features
s
s
Full militarized QED RM5261 microprocessor
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q
133,
s
High-performance floating point unit: up to 500 MFLOPS
cycle repeat rate for common single precision operations
and some double precision operations
q
Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q
Single cycle repeat rate for single precision combined multiply-
add operation
q
Single
150, 200, 250 MHz operating frequencies – Consult Factory
for latest speeds
q
345 Dhrystone 2.1 MIPS
q
SPECInt95 7.3, SPECfp95 8.3
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s
Pinout compatible with popular RM5260
High performance system interface compatible with RM5260,
RM 5270, RM5271, RM7000, R4600, R4700 and R5000
multiplexed system address/data bus for optimum price/
performance
q
High performance write protocols maximize uncached write
bandwidth
q
Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
q
IEEE 1149.1 JTAG boundary scan
q
64-bit
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• MIPS IV instruction set
point multiply-add instruction increases performance in
signal processing and graphics applications
q
Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Floating
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Embedded application enhancements
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Specialized
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• Integrated on-chip caches
q
32KB
DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
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instruction - 2 way set associative
q
32KB data - 2 way set associative
q
Virtually indexed, physically tagged
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Write-back and write-through on per page basis
q
Pipeline restart on first double for data cache misses
s
Fully static CMOS design with power down logic
reduced power mode with WAIT instruction
Watts typical power @ 200MHz
q
2.5V core with 3.3V IO’s
q
3.6
q
Standby
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208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
179-pin PGA package (Future
Product)
(P10)
• Integrated memory management unit
associative joint TLB (shared by I and D translations)
q
48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Fully
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Block Diagram
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5261 REV 1 12/22/98
DESCRIPTION
The Aeroflex ACT5261 is a highly integrated
superscalar microprocessor that implements a
superset of the MIPS IV Instruction Set
Architecture(ISA). It has a high performance 64-bit
integer unit, a high throughput, fully pipelined 64-bit
floating point unit, an operating system friendly
memory management unit with a 48-entry fully
associative TLB, a 32 KByte 2-way set associative
instruction cache, a 32 KByte 2-way set associative
data cache, and a high-performance 64-bit system
interface. The ACT5261 can issue both an integer
and a floating point instruction in the same cycle.
The ACT5261 is ideally suited for high-end
embedded
control
applications
such
as
internetworking,
high
performance
image
manipulation, high speed printing, and 3-D
visualization.
Integer Unit
Like the ACT5260, the ACT5261 implements the
MIPS IV Instruction Set Architecture, and is
therefore fully upward compatible with applications
that run on processors implementing the earlier
generation MIPS I-III instruction sets. Additionally,
the ACT5261 includes two implementation specific
instructions not found in the baseline MIPS IV ISA
but that are useful in the embedded market place.
Described in detail in the QED RM5261 datasheet,
these instructions are integer multiply-accumulate
and 3-operand integer multiply.
The ACT5261 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer multiply/divide operations, and the program
counter(PC).
HARDWARE OVERVIEW
The ACT5261 offers a high-level of integration
targeted
at
high-performance
embedded
applications. The key elements of the ACT5261 are
briefly described below.
Register File
The ACT5261 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
Superscalar Dispatch
The ACT5261 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-add, converts, etc. In combination with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT5261 provides unparalleled price/performance
in
computationally
intensive
embedded
applications.
ALU
The ACT5261 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perform all
operations in a single processor cycle.
CPU Registers
Like all MIPS ISA processors, the ACT5261 CPU
has a simple, clean user visible state consisting of
32 general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark™ RM 5261™, 64-Bit Superscalar
Microprocessor see the latest QED datasheet
(Revision 1.0 July 1998).
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5261 uses
the simple 5-stage pipeline also found in the
RM52xx family, 4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5261
uses an extended seven stage pipeline for
floating-point operations. Like the ACT5260, the
ACT5261 does virtual to physical translation in
parallel with cache access.
Aeroflex Circuit Technology
2
SCD5261 REV 1 12/22/98 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Sample Ordering Information
Part Number
ACT- 5261PC-133F17I
ACT- 5261PC-150F17C
ACT- 5261PC-200F17T
ACT-5261PC-250F17M
Screening
Industrial Temperature
Commercial Temperature
Military Temperature
Military Screening
Speed (MHz)
133
150
200
250
Package
208 Lead CQFP
208 Lead CQFP
208 Lead CQFP
208 Lead CQFP
Part Number Breakdown
ACT– 5261 PC – 200 F17 M
Aeroflex Circuit
Technology
Base Processor Type
Cache Style
PC = Primary Cache
Screening
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
*
Q = MIL-PRF-38534 Compliant/SMD if applicable
Package Type & Size
Maximum Pipeline Freq.
133 = 133MHz
150 = 150MHz
200 = 200MHz
250 = 250MHz
266 = 266MHz (Future Option)
Surface Mount Package
F17 = 1.120" SQ 208 Lead CQFP
F24 = 1.120" SQ Inverted 208 Lead CQFP
Thru-Hole Package
P10 = 1.86"SQ PGA 179 pins with shoulder (Advanced)
*
Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: (800) 843-1553
E-Mail: sales-act@aeroflex.com
5
SCD5261 REV 1 12/22/98 Plainview NY (516) 694-6700
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