M74HC155
DUAL 2 TO 4 LINE DECODER 3 TO 8 LINE DECODER
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 13ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 155
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HC155B1R
M74HC155M1R
DESCRIPTION
The M74HC155 is an high speed CMOS QUAD
2-INPUT NAND GATE fabricated with silicon gate
C
2
MOS technology.
It features dual 1 to 4 line demultiplexers with
individual strobe inputs (1G and 2G), individual
data inputs (1C and 2C) and common binary
address inputs (A and B).
When both decoders are enabled by the strobes,
the inverted output of 1C data and non-inverted
output of 2C data will be brought to the select
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
output pins of each sections. A 1 to 8 line
demultiplexer can also easily built up by providing
a data signal to both 1C and 2C inputs; the output
order from the msb is 1Y3, 1Y2, 1Y1, 1Y0, 2Y3,
2Y2, 2Y1, 2Y0. This device can be used as a 2 to
4 line decoder or a 3 to 8 line decoder when 1C is
held high and 2C is held low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
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M74HC155RM13TR
M74HC155TTR
s)
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T&R
July 2001
1/9
M74HC155
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
O
Supply Voltage
DC Input Voltage
b
O
I
CC
or I
GND
DC V
CC
or Ground Current
P
D
Power Dissipation
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
so
I
OK
te
le
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
r
P
uc
od
s)
t(
bs
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P
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t(
uc
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
500(*)
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
°
C; derate to 300mW by 10mW/
°
C from 65
°
C to 85
°
C
3/9
M74HC155
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
T
A
= 25°C
Min.
Typ.
5
53
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAY TIME
(f=1MHz; 50% duty cycle)
O
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
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5/9