Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
PHP50N06LT, PHB50N06LT, PHD50N06LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 55 V
I
D
= 50 A
g
s
R
DS(ON)
≤
24 mΩ (V
GS
= 5 V)
R
DS(ON)
≤
22 mΩ (V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP50N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N06LT is supplied in the SOT404 surface mounting package.
The PHD50N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate
drain
1
source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
±
13
50
35
200
125
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
PHP50N06LT, PHB50N06LT, PHD50N06LT
CONDITIONS
TYP.
-
MAX.
1.2
-
-
UNIT
K/W
K/W
K/W
SOT78 package, in free air
SOT404 and SOT428 package, pcb
mounted, minimum footprint
60
50
ESD LIMITING VALUE
SYMBOL PARAMETER
V
C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
(BR)GSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
I
G
=
±1
mA;
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 5 V; I
D
= 12.5 A
V
GS
= 10 V; I
D
= 12.5 A
T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
Gate source leakage current V
GS
=
±5
V; V
DS
= 0 V
T
j
= 175˚C
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
V
DS
= 55 V; V
GS
= 0 V;
T
j
= 175˚C
I
D
= 50 A; V
DD
= 44 V; V
GS
= 5 V
T
j
= -55˚C
MIN.
55
50
10
1.0
0.5
-
-
-
-
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
1.5
-
-
19
17
-
40
0.02
-
0.05
-
27
4
14
30
80
95
40
3.5
4.5
7.5
1500
300
150
-
-
-
2.0
-
2.3
24
22
50
-
1
20
10
500
-
-
-
45
130
135
55
-
-
-
2000
360
200
V
V
V
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 10
Ω
Resistive load
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
September 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
I
F
= 40 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
TYP. MAX. UNIT
-
-
0.95
1.0
40
0.07
50
200
1.2
-
-
-
A
A
V
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
-
MAX.
80
UNIT
mJ
Drain-source non-repetitive I
D
= 40 A; V
DD
≤
25 V; V
GS
= 5 V;
unclamped inductive turn-off R
GS
= 50
Ω;
T
mb
= 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
September 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
1000
ID / A
7524-55
40
RDS(ON)/mOhm
35
RDS(ON) = VDS / ID
100
VGS/V =
4
4.2
tp = 10 us
100 us
30
4.4
4.6
4.8
5
25
10
DC
1 ms
10 ms
100 ms
20
1
1
10
VDS / V
100
1000
15
10
15
20
25
30
35
40 45
ID/A
50
55
60
65
70
75
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Transient thermal impedance, Zth (K/W)
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
100
ID/A
80
10
1
0.5
0.2
0.1
0.05
0.02
P
D
t
p
D=
t
p
T
t
60
0.1
40
0.01
0
T
20
Tj/C = 175
0
25
0.001
10us
1ms
pulse width, tp (s)
0.1s
10s
0
1
2
3
VGS/V
4
5
6
7
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain current, ID (A)
10
8
6
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Transconductance, gfs (S)
40
100
VGS = 5.0 V
4.8
4.6
4.4
4.2
35
30
25
20
15
10
5
80
60
4.0
3.8
3.6
3.4
3.2
2.6
3.0
2.8
10
40
20
0
0
2
4
6
8
Drain-source voltage, VDS (V)
0
20
40
60
Drain current, ID (A)
80
100
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
September 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
2.5
a
BUK959-60
Rds(on) normlised to 25degC
3
2.5
2
Thousands pF
2
1.5
1.5
Ciss
1
1
0.5
0.5
-100
-50
0
50
Tmb / degC
100
150
200
0
0.01
0.1
1
VDS/V
10
Coss
Crss
100
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
BUK959-60
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
6
VGS/V
5
VDS = 14V
4
VDS = 44V
3
2.5
min.
1
2
0.5
1
0
-100
-50
0
50
Tj / C
100
150
200
0
0
5
10
15
QG/nC
20
25
30
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
100
IF/A
1E-01
1E-02
2%
typ
98%
80
1E-03
60
1E-04
40
Tj/C =
20
175
25
1E-05
1E-05
0
0
0.5
1
1.5
2
2.5
3
0
0.5
VSDS/V
1
1.5
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
September 1998
5
Rev 1.400
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