V58C2512804SDLH5DH datasheet, PDF

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V58C2512804SDLH5DH: DescriptionDDR DRAM, 64MX8, CMOS, PBGA144, ROHS COMPLIANT, MO-207, BGA-144; Categorystorage storage; File Size1MB，61 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V58C2512804SDLH5DH Overview

DDR DRAM, 64MX8, CMOS, PBGA144, ROHS COMPLIANT, MO-207, BGA-144

V58C2512804SDLH5DH Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	DSBGA
package instruction	TBGA,
Contacts	144
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B144
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	144
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
Base Number Matches	1

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V58C2512(804/404/164)SD

HIGH PERFORMANCE 512 Mbit DDR SDRAM

4 BANKS X 16Mbit X 8 (804)

4 BANKS X 32Mbit X 4 (404)

4 BANKS X 8Mbit X 16 (164)

DDR500

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

4ns

250 MHz

DDR400

6ns

5ns

200 MHz

DDR333

6ns

166 MHz

DDR266

7.5ns

133 MHz

Features

Description

The V58C2512(804/404/164)SD is a four bank DDR

DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x

32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The

V58C2512(804/404/164)SD achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

High speed data transfer rates with system frequency

up to 250MHz

Data Mask for Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2.5, 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 60 Ball FBGA AND 66 Pin TSOP II

SSTL-2 Compatible I/Os

Double Data Rate (DDR)

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

Differential clock inputs CK and CK

Power Supply 2.5V ± 0.2V

tRAS lockout supported

Concurrent auto precharge option is supported

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-4

•

Power

-75

•

-5

•

-6

•

Std.

•

Temperature

Mark

Blank

V58C2512(804/404/164)SD Rev.1.6 May 2010

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