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SYS8V512FK-020

Description
SRAM Module, 512KX8, 20ns, CMOS, PDMA32, PLASTIC, DIP-32
Categorystorage    storage   
File Size45KB,2 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

SYS8V512FK-020 Overview

SRAM Module, 512KX8, 20ns, CMOS, PDMA32, PLASTIC, DIP-32

SYS8V512FK-020 Parametric

Parameter NameAttribute value
Parts packaging codeMODULE
package instruction,
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time20 ns
JESD-30 codeR-PDMA-T32
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal locationDUAL
Base Number Matches1
512K x 8 SRAM MODULE
SYS8V512FK - 015/020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.3 : February 1999
Features
Access Times of 015/020/025/35 ns.
32 Pin 0.6" Dual-In-Line package with JEDEC
compatible pinout.
3.3 Volt Supply ± 10%.
Low Power Dissipation:
Operating
6.60 mW (maximum).
Standby (
-L Version
) 0.80 W (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL
compatible
On-board Supply Decoupling Capacitors.
Pin Definition
Description
The SYS8V512FK is plastic 4M Static RAM Module
housed in a standard 32 pin Dual-In-Line package
organised as 512K x 8. The module is designed to
operate at low Vcc (3.3V ± 10%).
The module utilises four fast 128Kx8 SRAMs
housed in SOJ packages, double sided surface
mount techniques, buried decoder and dual board
construction to achieve a very high density module.
The module has Chip Select, Write Enable and
Output Enable control inputs; the Output Enable
pin allows faster access times than address access
during a Read Cycle.
Block Diagram
AO - A 16
D0 - D7
WE
OE
128K x 8
SRAM
CS
128K x 8
SRAM
CS
128K x 8
SRAM
CS
128K x 8
SRAM
CS
DECODER
A17
CS
A18
Pin Functions
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
TOP VIEW
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
Ground
A0 ~ A18
D0 ~ D7
CS
WE
OE
V
CC
GND
Package Details
Plastic 32 Pin 0.6" JEDEC DIP

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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