UNISONIC TECHNOLOGIES CO., LTD
UR5596
DDR TERMINATION
REGULATOR
DESCRIPTION
The UTC
UR5596
is a linear bus termination regulator and
designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic)
specifications for termination of DDR-SDRAM. It also can be
used in SSTL-3 or HSTL (High-Speed Transceiver Logic)
scheme. The device contains a high-speed OP AMP to provide
excellent response to the load transients, and can deliver 1.5A
continuous current and transient peaks up to 3A in the application
as required for DDR-SDRAM termination.
The UTC
UR5596
also incorporates a V
SENSE
pin to provide
superior load regulation and a V
REF
output as a reference for the
chipset and DIMMs. Besides, an active low shutdown (SHDN) pin
provides Suspend To RAM (STR) functionality. When SHDN is
pulled low the V
TT
output will tri-state providing a high impedance
output, but, V
REF
will remain active. A power savings advantage
can be obtained in this mode through lower quiescent current.
Regarding the output, V
TT
is capable of sinking and sourcing
current while regulating the output voltage equal to V
DDQ
/2. The
output stage has been designed to maintain excellent load
regulation while preventing shoot through. The UTC
UR5596
also
incorporates two distinct power rails that separates the analog
circuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipation and
permits UTC
UR5596
to provide a termination solution for DDRII
SDRAM.
CMOS IC
*Pb-free plating product number: UR5596L
FEATURES
* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection
ORDERING INFORMATION
Ordering Number
Normal
Lead Free Plating
UR5596-S08-R
UR5596L-S08-R
UR5596-S08-T
UR5596L-S08-T
UR5596L-S08-R
(1) Packing Type
(2) Package Type
(3) Lead Plating
(1) R: Tape Reel, T: Tube
(2) S08: SOP-8
(3) L: Lead Free Plating, Blank: Pb/Sn
Package
SOP-8
SOP-8
Packing
Tape Reel
Tube
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QW-R502-045,B
UR5596
PIN DESCRIPTIONS
AV
IN
, PV
IN
CMOS IC
Input supply pins.
AV
IN
is used to supply all the internal analog circuits and PV
IN
is used to provide the output stage
to create V
TT
. These pins have the capability to work off separate supplies depending on the application. Higher
voltages on PV
IN
will increase the maximum continuous output current because of output RDSON limitations at
voltages close to V
TT
. But the internal power loss will also increase, thermally limiting the design. If the junction
temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual
shutdown where V
TT
is tri-stated and V
REF
remains active.
For SSTL-2 applications, a good compromise would be to connect the AV
IN
and PV
IN
directly together at 2.5V. This
eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is
that PV
IN
must be equal to or lower than AV
IN
. It is recommended to connect PV
IN
to voltage rails equal to or less
than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation.
V
DDQ
The input pin used to create the internal reference voltage from a resistor divider of two internal 50kΩ
resistors for
regulating V
TT
and to guarantee V
TT
will track V
DDQ
/2 precisely. As a remote sense by connecting V
DDQ
directly to the
2.5V rail for SSTL-2 applications is an optimal implementation of V
DDQ
at the DIMM. This ensures that the reference
voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines.
V
SENSE
The sense pin supply improved remote load regulation, if remote load regulation is not used then the V
SENSE
pin
must still be connected to V
TT
. A long trace will cause a significant IR drop resulting in a termination voltage lower at
one end of the bus than the other. Connect V
SENSE
pin to the middle of the bus to provide a better distribution across
the entire termination bus then DDR performance will be improved. Take notice of when a long V
SENSE
trace is
implemented in close proximity to the memory, noise pickup in the V
SENSE
trace can cause problems with precise
regulation of V
TT
. A ceramic capacitor of 0.1uF is placed to next the V
SENSE
pin can help filter any high frequency
signals and preventing errors.
V
REF
V
REF
supply the buffered output of the internal reference voltage V
DDQ
/2. This output delivers the reference voltage
for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be
little current drawn from V
REF
. A 0.1µF~0.01µF ceramic capacitor could be used to acquire better performance,
located close to the pin to help with noise. This output remains active during the shutdown state and thermal
shutdown events for the suspend to RAM functionality.
V
TT
V
TT
is a regulated output for the bus resistors termination of DDR-SDRAM. It can track precisely the V
DDQ
/2
voltage with the sinking and sourcing current capability. The UTC
UR5596
is designed to handle peak transient
currents of up to ± 3A with a fast transient response. If a transient is expected to remain above the maximum
continuous current rating for a significant amount of time then the output capacitor size should be large enough to
prevent an excessive voltage drop.
Although UTC
UR5596
can handle large transient output currents, but it can not handling these for long durations
since the limited thermal dissipation capability of SOP-8 package. If large currents are required for longer durations,
then must ensure the maximum junction temperature is not exceeded, otherwise, the maximum output current will be
degraded with heating. Proper thermal de-rating should always be used. While the temperature beyond the junction
temperature, the thermal shutdown protection will be functioned, then V
TT
will tri-state until the part returns below the
hysteretic trigger point.
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