DATASHEET
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
Description
The IDT5P49EE602 is a programmable clock generator
intended for low power, battery operated consumer
applications.There are four internal PLLs, each individually
programmable, allowing for up to six differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional
32.768kHz crystal oscillator is available to provide a real
time clock or non-critical performance MHz processor
clock.
The IDT5P49EE602 can be programmed through the use
of the I
2
C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
sepctrum mode.
There are total five 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
IDT5P49EE602
Features
•
Four internal PLLs
•
Internal non-volatile EEPROM
•
Internal I
2
C EEPROM master interface
•
FAST (400kHz) mode I
2
C serial interfaces
•
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
•
Output Frequency Ranges: kHz to 120 MHz
•
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
•
8-bit output-divider blocks
•
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
•
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
•
1.8V VDD Core Voltage
•
Available in 24pin 4x4mm QFN packages
•
-40 to +85 C Industrial Temp operation
Target Applications
•
•
•
•
•
•
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
1
IDT5P49EE602
REV L 111814
IDT5P49EE602
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Functional Block Diagram
VDD
VDDO1
VDDO2
VDDO3
X IN /R E F
R E F S E LA
XOUT
P LL A
S
R
C
0
S
R
C
1
S
R
C
2
S
R
C
3
/D IV 0
O UT0
R E FS E LB
P L LB (S S )
/D IV 1
O UT1
SDA
SCL
S E L [1:0 ]
C on trol
L ogic
R E F S E LC
P L LC
/D IV 2
O UT2
/D IV 3
O UT3
R E FS E LD
P L LD
S
R
C
4
O U T 4A
/D IV 4
O U T 4B
32 kX IN
32 kX O U T
GND
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
2
IDT5P49EE602
REV L 111814
IDT5P49EE602
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Pin Assignment
OUT4A
19
X1
GND
VDD
SDA
X2
OUT3
OUT2
SEL0
VDDO1
X132k
X232k
1
OUT4B
SCLK
VDDO3
OUT0
VDD
13
7
GND
GND
VDD
VDDO2
OUT1
VDDX
24- pin QFN
Pin Descriptions
Pin Name
OUT3
OUT2
SEL0*
VDDO1
Pin #
1
2
3
4
I/O
O
O
I
Pin Type
Adjustable
Adjustable
LVTTL
Power
SEL1
Pin Description
Configurable clock output 3. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configuration select pin. Weak internal pull down resistor.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4. VDDO1
must be greater than or equal to both VDDO2 and VDDO3.
32kHz CRYSTAL_IN -- Reference crystal input
32kHz CRYSTAL_OUT -- Reference crystal feedback.
Crystal oscillator power supply. Connect to 1.8V. Use filtered
analog power supply if available.
Connect to Ground.
Device power supply. Connect to 1.8V.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT3. VDDO2
must be equal or less than VDDO1.
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configuration select pin. Weak internal pull down resistor.
X132k
X232k
5
6
7
8
9
10
I
O
LVTTL
LVTTL
Power
Power
Power
Power
VDDx
GND
VDD
VDDO2
OUT1
SEL1*
11
12
O
I
Adjustable
LVTTL
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
3
IDT5P49EE602
REV L 111814
IDT5P49EE602
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
GND
13
14
15
16
O
Power
Power
Adjustable
Power
Connect to Ground.
Device power supply. Connect to 1.8V.
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0/3/6/7/8/9.
VDDO3 must be equal or less than VDDO1.
I
2
C clock. Logic levels set by VDDO1. 5V tolerant.
Configurable clock output 4B. Output voltage levels are
controlled by VDDO1.
Configurable clock output 4A. Output voltage levels are
controlled by VDDO1.
VDD
OUT0
VDDO3
SCLK
OUT4B
OUT4A
SDA
17
18
19
20
21
22
23
24
I
O
O
I/O
LVTTL
Adjustable
Adjustable
Open Drain Bidirectional I
2
C data. Logic levels set by VDDO1. 5V tolerant.
Power
Power
Device power supply. Connect to 1.8V.
Connect to Ground.
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum clock input voltage is 1.8V.
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
VDD
GND
XIN/ REF
XOUT
I
O
LVTTL
LVTTL
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above.
Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
Ideal Power Up Sequence
1) V
DD
and V
DD
x must come up first, followed by V
DD
O
2) V
DD
O1 must come up within 1ms after VDD and VDDX come up
3) V
DD
O2/3 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2/3 have approx. same ramp rate
Ideal Power Down Sequence
1) V
DD
O must drop first, followed by V
DD
and V
DD
x
2) V
DD
and V
DD
x must come down within 1ms after V
DD
O1 comes down
3) V
DD
O2/3 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2/3 have approx. same ramp rate
V
V
DD
O1
V
V
DD
O1
V
DD
O2, V
DD
O3
V
DD
, V
DD
x
V
DD
O2, V
DD
O3
V
DD
, V
DD
x
1 ms
t
1 ms
t
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
4
IDT5P49EE602
REV L 111814
IDT5P49EE602
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
PLL Features and Descriptions
D
VCO
M
XDIV
PLL Block Diagram
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
1 or 4
4
1 or 8 bit divide
1 or 4
Feedback
(M) Values
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
PLLA
PLLB
PLLC
PLLD
1 - 255
1 - 255
1 - 255
1 - 255
6 - 2047
6 - 2047
6 - 2047
6 - 2047
Yes
Yes
Yes
Yes
No
Yes
No
No
Crystal Input (XIN/REF)
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50 maximum equivalent series resonance. 0
ONXTALB=0 bit needs to be set for XIN/REF.
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The crystal cpacitors are internal to the device and have an
effective value of 4pF.
XDIV*M
F
OUT
= F
IN
*
(
)
D (Eq. 2)
ODIV
Where F
IN
is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and F
OUT
is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
5
IDT5P49EE602
REV L 111814
FPGA/CPLD
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EEWORLD
