WE32K32-XXX
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
Access Times of 125 and 150ns
MIL-STD-883 Compliant Devices Available
Packaging:
• 68 lead, Hermetic CQFP (G2U), 122.4mm (0.880")
square, 3.56mm (0.140") height (Package 510).
• 66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400)
Data Retention at 25°C, 10 Years
Write Endurance, 10,000 Cycles
Organized as 32Kx32; User Configurable 64Kx16 or
128Kx8
Commercial, Industrial and Military Temperature Ranges
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5 Volt Power Supply
Low Power CMOS, 10mA Standby Typical
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
* This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION FOR WE32K32N-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
13
A
14
NC
NC
NC
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
66
W E 1 # CS1#
OE#
A0-14
Pin Description
56
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
V
CC
GND
NC
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
W E 2 # CS2#
W E 3 # CS3#
W E 4 # CS4#
32K x 8
32K x 8
32K x 8
32K x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014
Rev. 9
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WE32K32-XXX
FIGURE 2 – PIN CONFIGURATION FOR WE32K32-XG2UX
Top View
NC
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
V
CC
Pin Description
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
V
CC
GND
NC
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
OE#
A0-14
32K x 8
32K x 8
32K x 8
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014
Rev. 9
© 2014 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
V
CC
A11
A12
A13
A14
NC
NC
CS1#
OE#
CS2#
NC
WE2#
WE3#
WE4#
NC
NC
NC
Block Diagram
W E 1 # CS1#
W E 2 # CS2#
W E 3 # CS3#
W E 4 # CS4#
32K x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
WE32K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
Symbol
T
A
T
S
T
G
V
G
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
Unit
°C
°C
V
V
CS#
H
L
L
X
X
X
OE#
X
L
H
H
X
L
TRUTH TABLE
WE#
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
T
A
= +25°C
Parameter
Address input capacitance
OE# capacitance
WE# capacitance
CS1-4# capacitance
Data I/O capacitance
Symbol
C
AD
C
OE
C
WE
C
CS
C
I/O
Conditions
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VI/O = 0 V, f = 1.0 MHz
Max
50
50
25
40
Unit
pF
pF
pF
pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current (x32)
Standby Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
Symbol
I
LI
I
LOx32
I
CCx32
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OU
T = GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IH
, OE# = V
IH
, f = 5MHz
I
OL
= 2.1mA, V
CC
= 4.5V
I
OH
= -400μA, V
CC
= 4.5V
-80
Min
Max
10
10
320
2.5
0.45
2.4
2.4
Min
-90
Max
10
10
250
2.5
0.45
2.4
-120
Min
Max
10
10
200
2.5
0.45
2.4
-150
Min
Max
10
10
150
2.5
0.45
Unit
μA
μA
mA
mA
V
V
FIGURE 3 – AC TEST CIRCUIT
Input Pulse Levels
Input Rise and Fall
AC TEST CONDITIONS
Parameter
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OL
Current Source
Input and Output Reference Level
Output Timing Reference Level
D.U.T.
C
eff
= 50 pf
V
Z
≈ 1.5V
(Bipolar Supply)
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
OH
Current Source
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014
Rev. 9
© 2014 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WE32K32-XXX
WRITE
A write cycle is initiated when OE# is high and a low pulse is on
WE# or CS# with CS# or WE# low. The address is latched on the
falling edge of CS# or WE# whichever occurs last. The data is
latched by the rising edge of CS# or WE#, whichever occurs
fi
rst.
A byte write operation will automatically continue to completion.
The WE# line transition from high to low also initiates an internal
150
μsec
delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150
μsec
time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE# line low. The write cycle begins
when the last of either CS# or WE# goes low.
AC WRITE CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
WRITE CYCLE
Write Cycle Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
Symbol
t
WC
t
AS
t
WP
t
CS
t
AH
t
DH
t
CSH
t
DS
t
WPH
t
OES
t
OEH
0
100
0
50
0
0
50
50
10
10
-80
Min
Max
10
0
100
0
50
0
0
50
50
10
10
Min
-90
Max
10
30
150
0
100
10
0
100
50
10
10
Min
-120
Max
10
30
150
0
100
10
0
100
50
10
10
Min
-150
Max
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014
Rev. 9
© 2014 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WE32K32-XXX
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
CS1-4#
t
CS
WE1-4#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
WE1-4#
t
CS
CS1-4#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014
Rev. 9
© 2014 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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