U62256SK07G1 datasheet, PDF - EEWORLD Datasheet

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U62256SK07G1: DescriptionStandard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.330 INCH, SOP-28; Categorystorage storage; File Size79KB，9 Pages; ManufacturerSimtek; Websitehttp://www.simtek.com

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U62256SK07G1 Overview

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.330 INCH, SOP-28

U62256SK07G1 Parametric

Parameter Name	Attribute value
package instruction	SOP,
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	18.1 mm
memory density	262144 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.75 mm
Base Number Matches	1

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U62256

Standard 32K x 8 SRAM

Features

32768x8 bit static CMOS RAM

Access times 70 ns, 100 ns

Common data inputs and

Description

The U62256 is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

- Read

- Standby

- Write

- Data Retention

The memory array is based on a

MIXMOS cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

The Read cycle is finished by the

falling edge of W, or by the rising

edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

data outputs

Three-state outputs

Typ. operating supply current

70 ns: 50 mA

100 ns: 40 mA

TTL/CMOS-compatible

Automatical reduction of power

dissipation in long Read Cycles

Power supply voltage 5 V + 10 %

Operating temperature ranges

0 to 70 °C

-40 to 85 °C

CECC 90000 Quality Standard

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity >100 mA

Package: SOP28 (330 mil)

Pin Configuration

Pin Description

A14

A12

DQ0

DQ1

DQ2

VSS

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A14

DQ0 - DQ7

VCC

VSS

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

Top View

November 01, 2001

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