PRELIMINARY
JUNE 2006
XR16V2552
REV. P1.0.0
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
GENERAL DESCRIPTION
The XR16V2552
1
(V2552) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 16 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2552 and XR16L2552. The V2552 register set
is compatible to the ST16C2552 and the XR16L2552.
It supports the Exar’s enhanced features of
selectable FIFO trigger level, automatic hardware
(RTS/CTS) and software (Xon/Xoff) flow control, and
a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 16 Mbps at 3.3 Volt with 4X
sampling clock. The V2552 is available in 44-pin
PLCC and 32-pin QFN packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
2.25 to 3.6 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to Exar’s XR16L2552 in the
44-PLCC package
•
Two independent UART channels
■
■
Register set identical to 16V2550
Data rate of up to
16 Mbps at 3.3 V,
and
12.5 Mbps at 2.5 V
with 4X sampling rate
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 16 bytes
Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16V2552 B
LOCK
D
IAGRAM
•
Alternate Function Register
•
Device Identification and Revision
•
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
•
44-PLCC and 32-QFN packages
* 5 Volt Tolerant Inputs
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset
UART Channel A
UART
Regs
8-bit Data
Bus
Interface
BRG
16 Byte TX FIFO
TX & RX
IR
ENDEC
2.25 to 3.6 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
16 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16V2552
PRELIMINARY
REV. P1.0.0
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
TXRDYA#
DSRA#
41
44
43
RIA#
D4
D3
D2
D1
D0
42
D5
D6
D7
A0
7
8
9
10
40
6
5
4
3
2
1
CTSA#
CDA#
VCC
39
38
37
36
35
RXA
TXA
DTRA#
RTSA#
MFA#
INTA
VCC
TXRDYB#
RIB#
XTAL1 11
GND 12
XTAL2 13
A1
14
XR16V2552
44-pin PLCC
34
33
32
31
A2 15
CHSEL 16
INTB 17
CS# 18
MFB# 19
IOW# 20
RESET 21
GND 22
RTSB# 23
IOR# 24
RXB 25
TXB 26
DTRB# 27
CTSB# 28
30 CDB#
29
DSRB#
31 D4
30 D3
29 D2
D1
32 D5
28
27
D0
26
25
24 RXA
23 TXA
22 RTSA#
21 INTA
20 GND
19 NC
18 NC
17 CTSB#
TXB 16
D6
D7
A0
XTAL1
XTAL2
A1
A2
CHSEL
1
2
3
4
5
6
7
8
RTSB# 13
IOW# 11
RESET 12
IOR# 14
RXB 15
CS# 10
9
XR16V2552
32-pin QFN
ORDERING INFORMATION
P
ART
N
UMBER
XR16V2552IL32
XR16V2552IJ
P
ACKAGE
32-pin QFN
44-Lead PLCC
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
INTB
2
CTSA#
VCC
PRELIMINARY
REV. P1.0.0
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN
P
IN
#
44-PLCC
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
7
6
3
2
1
32
31
30
29
28
27
14
15
14
10
9
8
7
6
5
4
3
2
24
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART chip select (active low). This function selects channel A or B in
accordance with the logical state of the CHSEL pin. This allows data to
be transferred between the user CPU and the V2552.
Channel Select - UART channel A or B is selected by the logical state
of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects
the UART channel B while a logic 1 selects UART channel A. Normally,
CHSEL could just be an address line from the user CPU such as A4.
Bit-0 of the Alternate Function Register (AFR) can temporarily override
CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially
useful during the initialization routine.
UART channel A Interrupt output (active high). A HIGH indicates chan-
nel A is requesting for service. For more details, see
Figures 17
-
22
.
UART channel B Interrupt output (active high). A HIGH indicates chan-
nel B is requesting for service. For more details, see
Figures 17
-
22
.
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2
.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 2.
IOW#
11
20
I
CS#
10
18
I
CHSEL
8
16
I
INTA
INTB
TXRDYA#
21
9
-
34
17
1
O
O
O
TXRDYB#
-
32
O
MODEM OR SERIAL I/O INTERFACE
TXA
23
38
O
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
3
XR16V2552
Pin Description
N
AME
RXA
32-QFN
P
IN
#
24
44-PLCC
P
IN
#
39
T
YPE
I
PRELIMINARY
REV. P1.0.0
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
D
ESCRIPTION
UART channel A Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6] and MCR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
UART channel A Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If this pin is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Multi-Function Output Channel A. This output pin can function as the
OP2A#, BAUDOUTA#, or RXRDYA# pin. One of these output signal
functions can be selected by the user programmable bits 1-2 of the
Alternate Function Register (AFR). These signal functions are
described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is LOW
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults
to a logic 0 condition after a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the Baud
rate clock output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring block
data transfers. See
Table 2
for more details.
RTSA#
22
36
O
CTSA#
25
40
I
DTRA#
DSRA#
-
-
37
41
O
I
CDA#
-
42
I
RIA#
-
43
I
MFA#
-
35
O
TXB
16
26
O
UART channel B Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6] and MCR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
RXB
15
25
I
4
PRELIMINARY
REV. P1.0.0
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
Pin Description
N
AME
RTSB#
32-QFN
P
IN
#
13
44-PLCC
P
IN
#
23
T
YPE
O
D
ESCRIPTION
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], and IER[6].
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If this pin is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Multi-Function Output Channel B. This output pin can function as the
OP2B#, BAUDOUTB#, or RXRDYB# pin. One of these output signal
functions can be selected by the user programmable bits 1-2 of the
Alternate Function Register (AFR). These signal functions are
described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW
when MCR bit-3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a
logic 0 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the Baud
rate clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring block
data transfers. See
Table 2
for more details.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
4
5
12
11
13
21
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter out-
put will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see Table 15).
2.25 to 3.6V power supply. All input pins are 5V tolerant.
Power supply common, ground.
No Connect.
CTSB#
17
28
I
DTRB#
DSRB#
-
-
27
29
O
I
CDB#
-
30
I
RIB#
-
31
I
MFB#
-
19
O
VCC
GND
NC
26
20
18, 19
44, 33
22, 12
-
Pwr
Pwr
-
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
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