W83977ATF-P datasheet, PDF - EEWORLD Datasheet

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W83977ATF-P: DescriptionMultifunction Peripheral, CMOS, PQFP128, PLASTIC, QFP-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，212 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W83977ATF-P Overview

Multifunction Peripheral, CMOS, PQFP128, PLASTIC, QFP-128

W83977ATF-P Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	FQFP, QFP128,.67X.93,20
Contacts	128
Reach Compliance Code	unknown
Address bus width	16
boundary scan	NO
Bus compatibility	PC-XT; PC-AT; ISA; PS/2
maximum clock frequency	48 MHz
External data bus width	8
JESD-30 code	R-PQFP-G128
length	20 mm
Number of I/O lines	8
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.32 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
Base Number Matches	1

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W83977ATF

WINBOND I/O

W83977ATF

TABLE OF CONTENTS

GENERAL DESCRIPTION.................................................................................................................................1

FEATURES............................................................................................................................................................2

PIN CONFIGURATION ......................................................................................................................................5

1.0 PIN DESCRIPTION......................................................................................................................................6

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

OST

NTERFACE

...............................................................................................................................................6

ENERAL

URPOSE

I/O P

ORT

............................................................................................................................9

ERIAL

ORT

NTERFACE

.................................................................................................................................10

NFRARED

NTERFACE

.....................................................................................................................................11

ULTI

-M

ODE

ARALLEL

ORT

.......................................................................................................................11

FDC I

NTERFACE

..............................................................................................................................................16

KBC I

NTERFACE

.............................................................................................................................................17

POWER PINS ................................................................................................................................................18

ACPI I

NTERFACE

............................................................................................................................................18

2.0 FDC FUNCTIONAL DESCRIPTION .......................................................................................................19

2.1 W83977ATF FDC ..........................................................................................................................................19

2.1.1 AT interface .............................................................................................................................................19

2.1.2 FIFO (Data) ............................................................................................................................................19

2.1.3 Data Separator ........................................................................................................................................20

2.1.4 Write Precompensation ...........................................................................................................................20

2.1.5 Perpendicular Recording Mode ..............................................................................................................20

2.1.6 FDC Core ................................................................................................................................................21

2.1.7 FDC Commands ......................................................................................................................................21

2.2 R

EGISTER

ESCRIPTIONS

.................................................................................................................................31

2.2.1 Status Register A (SA Register) (Read base address + 0) .......................................................................31

2.2.2 Status Register B (SB Register) (Read base address + 1) .......................................................................33

2.2.3 Digital Output Register (DO Register) (Write base address + 2) ...........................................................35

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)..................................................................35

2.2.5 Main Status Register (MS Register) (Read base address + 4) ................................................................36

2.2.6 Data Rate Register (DR Register) (Write base address + 4)...................................................................36

2.2.7 FIFO Register (R/W base address + 5)...................................................................................................38

2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................................40

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)...............................................41

3.0 UART PORT.................................................................................................................................................43

3.1 U

NIVERSAL

SYNCHRONOUS

ECEIVER

RANSMITTER

(UART A, UART B)...............................................43

3.2 R

EGISTER

DDRESS

.........................................................................................................................................43

3.2.1 UART Control Register (UCR) (Read/Write) ..........................................................................................43

3.2.2 UART Status Register (USR) (Read/Write)..............................................................................................45

3.2.3 Handshake Control Register (HCR) (Read/Write) ..................................................................................46

Publication Release Date: October 2001

Revision 0.53

-I-

W83977ATF

3.2.4

3.2.5

3.2.6

3.2.7

3.2.8

3.2.9

Handshake Status Register (HSR) (Read/Write)......................................................................................47

UART FIFO Control Register (UFR) (Write only)..................................................................................48

Interrupt Status Register (ISR) (Read only).............................................................................................49

Interrupt Control Register (ICR) (Read/Write) .......................................................................................50

Programmable Baud Generator (BLL/BHL) (Read/Write) .....................................................................50

User-defined Register (UDR) (Read/Write).............................................................................................51

4.0 INFRARED (IR) PORT...............................................................................................................................52

4.1 IR R

EGISTER

ESCRIPTION

.............................................................................................................................52

4.2 S

0-L

EGACY

DVANCED

IR C

ONTROL AND

TATUS

EGISTERS

..................................................................53

4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ........................................53

4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)..........................................................................................54

4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)..........................................55

4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ...........................................................59

4.2.5 Set0.Reg4 - Handshake Control Register (HCR).....................................................................................59

4.2.6 Set0.Reg5 - IR Status Register (USR) ......................................................................................................61

4.2.7 Set0.Reg6 - Reserved ...............................................................................................................................62

4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)...................................................................................62

4.3 S

1 - L

EGACY

AUD

ATE

IVISOR

EGISTER

.............................................................................................63

4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)...............................................................................63

4.3.2 Set1.Reg 2~7............................................................................................................................................64

4.4 S

2 - I

NTERRUPT

TATUS

IR FIFO C

ONTROL

EGISTER

(ISR/UFR) .......................................................64

4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) .................................................................64

4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1) ..................................................................................64

4.4.3 Reg3 - Sets Select Register (SSR) ............................................................................................................65

4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2) ..................................................................................66

4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only).......................................................................68

4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only) ...........................................................................68

4.5 S

3 - V

ERSION

AND

APPED

ONTROL

EGISTERS

.................................................................................68

4.5.1 Reg0 - Advanced IR ID (AUID)...............................................................................................................68

4.5.2 Reg1 - Mapped IR Control Register (MP_UCR).....................................................................................69

4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR)...........................................................................69

4.5.4. Reg3 - Sets Select Register (SSR) ...........................................................................................................69

4.6 S

4 - TX/RX/T

IMER COUNTER REGISTERS

AND

CONTROL REGISTERS

. .....................................................69

4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)..............................................................................70

4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL)...........................................................................................70

4.6.3 Set4.Reg3 - Set Select Register (SSR) ......................................................................................................70

4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH)...................................................................71

4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) .......................................................................71

4.7 S

5 - F

LOW CONTROL

AND

CONTROL

AND

RAME

TATUS

FIFO

REGISTERS

...........................................71

4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) ..............................72

4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)............................................................................72

4.7.3 Set5.Reg3 - Sets Select Register (SSR).....................................................................................................72

4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1).............................................................................73

4.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO).................................................................................73

4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU)......74

4.8 S

6 - IR P

HYSICAL

AYER

ONTROL

EGISTERS

.........................................................................................75

4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)...........................................................................75

4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ..............................................................................76

4.8.3 Set6.Reg2 - SIR Pulse Width....................................................................................................................76

4.8.4 Set6.Reg3 - Set Select Register ................................................................................................................77

Publication Release Date: Apr 2001

Revision 0.53

- II -

W83977ATF

4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU)................................................77

4.9 S

7 - R

EMOTE CONTROL AND

MODULE SELECTION REGISTERS

.................................................................78

4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC)....................................................................78

4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) ...............................................................80

4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)......................................................................81

4.9.4 Set7.Reg3 - Sets Select Register (SSR).....................................................................................................82

4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1)...............................................................82

4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2)...............................................................83

4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3)...............................................................83

4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)......................................................................84

5.0 PARALLEL PORT .....................................................................................................................................85

5.1 P

RINTER

NTERFACE

OGIC

.............................................................................................................................85

5.2 E

NHANCED

ARALLEL

ORT

(EPP) .................................................................................................................86

5.2.1 Data Swapper ..........................................................................................................................................87

5.2.2 Printer Status Buffer................................................................................................................................87

5.2.3 Printer Control Latch and Printer Control Swapper ..............................................................................88

5.2.4 EPP Address Port....................................................................................................................................88

5.2.5 EPP Data Port 0-3 ..................................................................................................................................89

5.2.6 Bit Map of Parallel Port and EPP Registers...........................................................................................89

5.2.7 EPP Pin Descriptions..............................................................................................................................90

5.2.8 EPP Operation ........................................................................................................................................90

5.3 E

XTENDED

APABILITIES

ARALLEL

(ECP) P

ORT

..........................................................................................91

5.3.1 ECP Register and Mode Definitions........................................................................................................91

5.3.2 Data and ecpAFifo Port ..........................................................................................................................92

5.3.3 Device Status Register (DSR) ..................................................................................................................92

5.3.4 Device Control Register (DCR)...............................................................................................................93

5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ........................................................................................94

5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ...............................................................................................94

5.3.7 tFifo (Test FIFO Mode) Mode = 110 ......................................................................................................94

5.3.8 cnfgA (Configuration Register A) Mode = 111 .......................................................................................94

5.3.9 cnfgB (Configuration Register B) Mode = 111 .......................................................................................94

5.3.10 ecr (Extended Control Register) Mode = all .........................................................................................95

5.3.11 Bit Map of ECP Port Registers..............................................................................................................97

5.3.12 ECP Pin Descriptions............................................................................................................................98

5.3.13 ECP Operation ......................................................................................................................................99

5.3.14 FIFO Operation.....................................................................................................................................99

5.3.15 DMA Transfers ....................................................................................................................................100

5.3.16 Programmed I/O (NON-DMA) Mode..................................................................................................100

5.4 E

XTENSION

FDD M

ODE

(EXTFDD)............................................................................................................. 100

5.5 E

XTENSION

2FDD M

ODE

(EXT2FDD).........................................................................................................100

6.0 KEYBOARD CONTROLLER.................................................................................................................. 101

6.1 O

UTPUT

UFFER

............................................................................................................................................ 101

6.2 I

NPUT

UFFER

...............................................................................................................................................101

6.3 S

TATUS

EGISTER

.........................................................................................................................................102

6.4 C

OMMANDS

................................................................................................................................................... 102

6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC .......................................................104

6.5.1 KB Control Register (Logic Device 5, CR-F0)......................................................................................104

6.5.2 Port 92 Control Register (Default Value = 0x24) .................................................................................105

7.0 GENERAL PURPOSE I/O ........................................................................................................................ 106

Publication Release Date: Apr 2001

Revision 0.53

- III -

W83977ATF-P Related Products

	W83977ATF-P	W83977ATF-A
Description	Multifunction Peripheral, CMOS, PQFP128, PLASTIC, QFP-128	Multifunction Peripheral, CMOS, PQFP128, PLASTIC, QFP-128
Parts packaging code	QFP	QFP
package instruction	FQFP, QFP128,.67X.93,20	FQFP, QFP128,.67X.93,20
Contacts	128	128
Reach Compliance Code	unknown	unknown
Address bus width	16	16
boundary scan	NO	NO
Bus compatibility	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2
maximum clock frequency	48 MHz	48 MHz
External data bus width	8	8
JESD-30 code	R-PQFP-G128	R-PQFP-G128
length	20 mm	20 mm
Number of I/O lines	8	8
Number of terminals	128	128
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20	QFP128,.67X.93,20
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
power supply	5 V	5 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.32 mm	3.32 mm
Maximum supply voltage	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	14 mm	14 mm
Base Number Matches	1	1

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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