W83977AF-P datasheet, PDF - EEWORLD Datasheet

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W83977AF-P: DescriptionMicro Peripheral IC, PQFP128,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size940KB，184 Pages; ManufacturerNuvoton Technology Corporation; Websitehttp://www.nuvoton.com.cn/hq/

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W83977AF-P Overview

Micro Peripheral IC, PQFP128,

W83977AF-P Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QFP, QFP128,.67X.93,20
Reach Compliance Code	compliant
JESD-30 code	R-PQFP-G128
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Base Number Matches	1

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WINBOND I/O

W83977F-A/W83977G-A

W83977AF-A/W83977AG-A

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A

Table of Contents-

1. GENERAL DESCRIPTION ................................................................................................................ 1

2. FEATURES ........................................................................................................................................ 2

3. PIN CONFIGURATION...................................................................................................................... 5

4. PIN DESCRIPTION ........................................................................................................................... 6

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.1

Host Interface.......................................................................................................................... 6

Advanced Power Management............................................................................................... 8

Serial Port Interface ................................................................................................................ 9

Infrared Interface................................................................................................................... 10

Multi-Mode Parallel Port........................................................................................................ 11

FDC Interface........................................................................................................................ 15

KBC Interface........................................................................................................................ 16

RTC Interface........................................................................................................................ 16

POWER PINS ....................................................................................................................... 16

W83977F/G and W83977AF/AG FDC .................................................................................. 17

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

AT interface ............................................................................................................................17

FIFO (Data) ............................................................................................................................17

Data Separator .......................................................................................................................18

Write Precompensation ..........................................................................................................18

Perpendicular Recording Mode ..............................................................................................18

FDC Core ...............................................................................................................................19

FDC Commands.....................................................................................................................19

Status Register A (SA Register) (Read base address + 0).....................................................28

Status Register B (SB Register) (Read base address + 1).....................................................30

Digital Output Register (DO Register) (Write base address + 2) ............................................31

Tape Drive Register (TD Register) (Read base address + 3).................................................31

Main Status Register (MS Register) (Read base address + 4)...............................................33

Data Rate Register (DR Register) (Write base address + 4) ..................................................33

FIFO Register (R/W base address + 5) ..................................................................................34

Digital Input Register (DI Register) (Read base address + 7).................................................36

Configuration Control Register (CC Register) (Write base address + 7) ................................38

5. FDC FUNCTIONAL DESCRIPTION................................................................................................ 17

5.2

Register Descriptions ............................................................................................................ 27

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

6. UART PORT .................................................................................................................................... 39

6.1

6.2

Universal Asynchronous Receiver/Transmitter (UART A, UART B) .................................... 39

Register Address................................................................................................................... 39

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

UART Control Register (UCR) (Read/Write) ..........................................................................39

UART Status Register (USR) (Read/Write) ............................................................................41

Handshake Control Register (HCR) (Read/Write) ..................................................................42

Handshake Status Register (HSR) (Read/Write)....................................................................43

UART FIFO Control Register (UFR) (Write only)....................................................................44

-II

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A

6.2.6

6.2.7

6.2.8

6.2.9

Interrupt Status Register (ISR) (Read only) ............................................................................45

Interrupt Control Register (ICR) (Read/Write).........................................................................46

Programmable Baud Generator (BLL/BHL) (Read/Write).......................................................46

User-defined Register (UDR) (Read/Write) ............................................................................47

7. INFRARED (IR) PORT..................................................................................................................... 48

7.1

7.2

IR Register Description ......................................................................................................... 48

Set0-Legacy/Advanced IR Control and Status Registers..................................................... 49

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) .......................49

Set0.Reg1 - Interrupt Control Register (ICR)..........................................................................50

Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) ..........................51

Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): .........................................55

Set0.Reg4 - Handshake Control Register (HCR) ...................................................................55

Set0.Reg5 - IR Status Register (USR) ...................................................................................57

Set0.Reg6 - Reserved ............................................................................................................57

Set0.Reg7 - User Defined Register (UDR/AUDR) ..................................................................57

Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...............................................................59

Set1.Reg 2~7 .........................................................................................................................59

Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ..................................................60

Reg2 - Advanced IR Control Register 1 (ADCR1) ..................................................................60

Reg3 - Sets Select Register (SSR).........................................................................................61

Reg4 - Advanced IR Control Register 2 (ADCR2) ..................................................................61

Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ........................................................63

Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)............................................................63

Reg0 - Advanced IR ID (AUID)...............................................................................................63

Reg1 - Mapped IR Control Register (MP_UCR) .....................................................................64

Reg2 - Mapped IR FIFO Control Register (MP_UFR) ............................................................64

Reg3 - Sets Select Register (SSR).........................................................................................64

Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH) .............................................................64

Set4.Reg2 - Infrared Mode Select (IR_MSL) ..........................................................................65

Set4.Reg3 - Set Select Register (SSR) ..................................................................................65

Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ...................................................65

Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) ......................................................66

Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) .................66

Set5.Reg2 - Flow Control Mode Operation (FC_MD) .............................................................67

Set5.Reg3 - Sets Select Register (SSR) ................................................................................68

Set5.Reg4 - Infrared Configure Register 1 (IRCFG1).............................................................68

Set5.Reg5 - Frame Status FIFO Register (FS_FO) ...............................................................69

7.3

Set1 - Legacy Baud Rate Divisor Register ........................................................................... 59

7.3.1

7.3.2

7.4

Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)............................................ 59

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.5

Set3 - Version ID and Mapped Control Registers................................................................. 63

7.5.1

7.5.2

7.5.3

7.5.4

7.6

Set4 - TX/RX/Timer counter registers and IR control registers. ........................................... 64

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.7

Set 5 - Flow control and IR control and Frame Status FIFO registers.................................. 66

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

-III -

Publication Release Date: May 2006

Revision 0.60

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