2-05M
W42C32-05M
Spread Spectrum Frequency Timing Generator
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Generates a spread spectrum timing signal
• Reduces measured EMI by as much as 12 dB
• Integrated loop filter components
• Requires a single low-cost fundamental crystal (or
other frequency reference) for proper operation
• Special spread spectrum control functions
• Low-power CMOS design
• Power-down mode reduces current consumption and
disables the clock outputs
• Available in 16-pin SOIC package (300 mil)
Key Specifications
Cycle-to-Cycle Jitter .................................................... 250 ps
45/55 Duty Cycle .................................... approximately 1.4V
Selectable Frequency spread
2 ns rise/fall time 0.4V to 2.0V, 3.3V supply
2 ns rise/fall time 0.8V to 2.4V, 5.0V supply
Table 1. Frequency Spread Selection
W42C32-05M
FS2
0
0
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
14.318
REFOUT
(MHz)
22.1148
22.1148
14.7456
18.432
14.318
CLKOUT
(MHz)
44.2296 ±
2.5%
44.2296
±1.5%
29.4912 ±
2.5%
18.432 ± 2.5%
66.66 – 2%
Reserved
100 – 2%
Reserved
VDD
(V)
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
Overview
The W42C32-05M modulates the output of a single PLL in
order to ‘spread’ the bandwidth of a synthesized clock and,
more importantly, decrease the peak amplitudes of its funda-
mental harmonics. Since peak amplitudes are reduced, the
radiated electromagnetic emissions of the W42C32-05M are
significantly lower than the typical narrow band signal pro-
duced by oscillators and most frequency generators. Lowering
a signal’s amplitude by increasing its bandwidth is a method of
reducing EMI called ‘spread spectrum frequency timing gen-
eration’. This patented technique not only reduces the emis-
sions of the primary clock, but also impacts every signal syn-
chronized to it.
0
0
1
1
1
1
Pin Configuration
SOIC
PD#
X1
X2
GND
AGND
FS0
TEST
CLKOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFOUT
FS2
FS1
SSON#
RESET
VDD
AVDD
REFEN#
W42C32-05M
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
January 5, 2001, rev. **
W42C32-05M
Pin Definitions
[1]
Pin Name
CLKOUT
REFOUT
X1
Pin No.
8
16
2
Pin
Type
O
O
I
Pin Description
Output Modulated Frequency:
Frequency is set using FS0:2 (refer to
Table 1).
Reference Output:
A buffered version of the input frequency.
Crystal Connection or External Reference Frequency Input:
This pin has dual func-
tions. It can be used as either an external crystal connection, or as an external reference
frequency input.
Crystal Connection:
If using an external reference, this pin must be left unconnected.
Spread Spectrum Control (active LOW):
Pulling this input signal HIGH turns the internal
modulating waveform off. This pin has an internal pull-down resistor.
Frequency Selection Bit 0:
This pin selects the frequency and spreading characteristics.
Refer to
Table 1.
This pin has an internal pull-up resistor.
Frequency Selection Bit 1:
This pin selects the frequency and spreading characteristics.
Refer to
Table 1.
This pin has an internal pull-up resistor.
Frequency Selection Bit 2:
This pin selects the frequency and spreading characteristics.
Refer to
Table 1
(note the V
DD
specification). This pin has an internal pull-up resistor.
Power-down (active LOW):
Enabling power-down reduces current consumption and
disables the clock outputs. This pin has an internal pull-up resistor.
Reference Clock Selection Input:
Pulling this signal LOW turns the REFOUT clock
output on. This pin has an internal pull-up resistor.
[1]
Reset:
A reset starts the spread spectrum modulating frequency at the beginning point
of the modulation profile. This pin has an internal pull-down resistor. To reset the spread
spectrum modulating frequency, pull this pin from LOW to HIGH.
Power Connection:
Connected to either 3.3V or 5.0V power supply. V
DD
and AV
DD
must
be the same voltage level.
Analog Power Connection:
Connected to either 3.3V or 5.0V power supply. V
DD
and
AV
DD
must be the same voltage level.
Ground Connection:
Connect to the common system ground plane.
Analog Ground Connection:
Connect to the common system ground plane.
Three-state Input:
Pulling this input pin and REFEN# pin HIGH, CLKOUT will be
three-stated. This pin has an internal pull-down resistor.
[2]
X2
SSON#
FS0
FS1
FS2
PD#
REFEN#
RESET
3
13
6
14
15
1
9
12
I
I
I
I
I
I
I
I
VDD
AVDD
GND
AGND
TEST
11
10
4
5
7
P
P
G
G
I
Notes:
1. Pull-up resistors not CMOS level.
2. Pulling PD# and REFEN# input pins HIGH, REFOUT will be three-stated.
2
W42C32-05M
Functional Description
The W42C32-05M uses a Phase Locked Loop (PLL) to multi-
ply the frequency of a low-cost, low-frequency crystal up to the
desired clock frequency. The basic circuit topology is shown in
Figure 1.
An on-chip crystal driver causes the crystal to oscil-
late at its fundamental. The resulting reference signal is divid-
ed by Q and fed to the phase detector. The VCO output is
divided by P and also fed back to the phase detector. The PLL
will force the frequency of the VCO output signal to change
until the divided output signal and the divided reference signal
match at the phase detector input. The output frequency is
then equal to the ratio of P/Q times the reference frequency.
The unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum frequency timing generation, EMI reduc-
tion depends on the shape, modulation percentage, and fre-
quency of the modulating waveform. While the shape and fre-
quency of the modulating waveform in the W42C32 are fixed,
the modulation percentage may be varied.
Using frequency select bits (FS2:0 pins), various spreading
percentages for different input frequency ranges can be cho-
sen. For example, refer to the W42C32-05M in
Table 1.
If the
logic level on FS2:0 = 000, then an input reference frequency
between 14 and 24 MHz will produce an output frequency at
twice the reference frequency with a spread of ±2.5%.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.875% and ±2.5% are
most common.
Additional Features of the W42C32-05M
A RESET pin is available to aid in applications which have
multiple PLL clock generators. When a reset is issued, the
modulation profile shown in
Figure 3
is reset to its starting
point. This feature is necessary for applications in which two
spread spectrum systems must synchronize with each other.
The REFOUT out pin provides a buffered version of the input
clock frequency.
The SSON# pin disables the spread spectrum function when
set to logic HIGH. Otherwise, an internal pull-down resistor
leaves this feature enabled.
The PD# pin reduces power consumption and disables the
clock outputs when set to logic LOW. Otherwise, an internal
pull-up resistor places the W42C32-05M into normal mode.
V
DD
X1
XTAL
X2
Freq.
Divider
Q
Phase
Detector
Charge
Pump
CLKOUT
Σ
VCO
Post
Dividers
Modulating
Waveform
Crystal load
capacitors
as needed
Feedback
Divider
P
PLL
GND
Figure 1. System Block Diagram (Concept, not actual implementation)
3
W42C32-05M
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in
Figure 2.
An EMI emission profile
of a clock harmonic is shown.
5dB/div
SSFTG
Typical Clock
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in
Figure 3.
The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
f
Center
±
X
MOD
% in the frequency spread selection table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is f
MAX
–
X
MOD
%. Whenever this expression is used,
Cypress has taken care to ensure that f
MAX
will never be ex-
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
Amplitude (dB)
Figure 2. Typical Clock and SSFTG Comparison
90%
100%
10%
Contrast the typical clock EMI with the Cypress spread spec-
trum clock. Notice the spike in the typical clock. This spike can
make systems fail quasi-peak EMI testing. The FCC and other
regulatory agencies test for peak emissions. With Cypress’s
Spread Spectrum Frequency Timing Generator (SSFTG), the
peak energy is much lower (at least 8 dB) because the energy
is spread out across a wider bandwidth.
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 3. Modulation Waveform Profile
4
100%
W42C32-05M
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
Unit
V
°C
°C
°C
DC Electrical Characteristics:
0°C < T
A
< 70°C, V
DD
= 5.0V±10%, 3.3V±5%
Parameter
I
DD
I
PD
t
OFF
t
ON
t
EN
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
C
L
R
P
Z
OUT
Description
Supply Current
Power Down Supply Current
Power Down Time
Power Up Time
Enable/Disable Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
XTAL Load Capacitance
Input Pull-Up Resistor
Clock Output Impedance
@ 0.4V, V
DD
= 3.3V
@ 2.4V, V
DD
= 3.3V
All pins except X1, X2
Pins X1, X2
V
IN
= 0V
Any clock output pin
300
33
2.4
2.4
7
16
V
DD
= 5.0V
V
DD
= 3.3V
2.4
2.4
–100
10
First locked clock cycle after
PD# goes HIGH
Time required for output to be
enabled/disabled
V
DD
= 5.0V
V
DD
= 3.3V
V
DD
= 5.0V
V
DD
= 3.3V
3.0
0.7V
DD
0.4
Test Condition
V
DD
= 5.0V
V
DD
= 5.0V
Min.
Typ.
35
Max.
45
75
4
5
4
0.8
0.15V
DD
Unit
mA
µA
cycles
[3]
ms
cycles
[3]
V
V
V
V
V
V
V
µA
µA
mA
mA
pF
pF
kΩ
Ω
Note:
3. Cycle refers to input clock cycles supplied by the input crystal or reference.
5
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