CY7C1380F-250BZXC datasheet, PDF

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CY7C1380F-250BZXC: DescriptionCache SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; Categorystorage storage; File Size1MB，34 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1380F-250BZXC Overview

Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1380F-250BZXC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.07 A
Maximum slew rate	0.35 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13 mm
Base Number Matches	1

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM

Features

■

Functional Description

The

CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

[1]

SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive edge triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE

depth-expansion chip enables (CE

and CE

3 [2]

), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW

, and BWE),

and global write (GW). Asynchronous inputs include the output

enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as they are controlled by the advance pin

(ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see

Table 1

on page 6 and

“Truth Table”

on page 10

for further details). Write cycles can be one to two or four bytes

wide as controlled by the byte write control inputs. GW when

active LOW causes all bytes to be written.

The

CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

operates from a +3.3V core power supply while all outputs

operate with a +2.5 or +3.3V power supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

3.3V core power supply

2.5V or 3.3V I/O power supply

Fast clock-to-output times

❐

2.6 ns (for 250 MHz device)

Provides high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel Pentium

inter-

leaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self-timed write

Asynchronous output enable

Single cycle chip deselect

CY7C1380D/CY7C1382D is available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA

package; CY7C1380F/CY7C1382F is available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 119-ball BGA and 165-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

ZZ sleep mode option

■

Selection Guide

Description

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

250 MHz

2.6

350

200 MHz

3.0

300

167 MHz

3.4

275

Unit

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064,

SRAM System Design Guidelines

www.cypress.com.

2. CE

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation

Document #: 38-05543 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 12, 2009

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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