High Performance
256K×4
CMOS SRAM
AS7C1028
AS7C1028L
®
256K×4 CMOS SRAM
Features
• Organization: 262,144 words × 4 bits
• High speed
- 12/15/20/25/35 ns address access time
- 4/4/5/6/8 ns output enable access time
• Low power consumption
- Active: 660 mW max (15 ns cycle)
- Standby: 27.5 mW max, CMOS I/O
5.5 mW max, CMOS I/O, L version
- Very low DC component in active power
• 2.0V data retention (L version)
• Equal access and cycle times
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil PDIP and SOJ
- 400 mil PDIP and SOJ
• ESD protection > 2000 volts
• Latch-up current > 200 mA
Logic block diagram
Vcc
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
Pin arrangement
DIP, SOJ
Row decoder
512×512×4
Array
(1,048,576)
Sense amp
I/O2
I/O1
I/O0
Column decoder
WE
Control
circuit
OE
CE
A A A A A A A A A
9 10 11 12 13 14 15 16 17
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
L
7C1028-12
12
4
130
5.0
1.0
7C1028-15
15
4
120
5.0
1.0
7C1028-20
20
5
110
5.0
1.0
7C1028-25
25
6
100
5.0
1.0
AS7C1028
I/O3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A17
A16
A15
A14
A13
A12
A11
NC
I/O0
I/O1
I/O2
I/O3
WE
7C1028-35
35
8
80
5.0
1.0
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
AS7C1028
AS7C1028L
Functional description
The AS7C1028 is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 262,144 words × 4 bits. It
is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20/25/35 ns with output enable access times (t
OE
) of 4/4/5/6/8 ns are ideal
for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
When CE is HIGH the device enters standby mode. The standard AS7C1028 is guaranteed not to exceed 27.5 mW power consumption in
standby mode; the L version is guaranteed not to exceed 5.5 mW, and typically requires only 800 µW. The L version also offers 2.0V data
retention, with maximum power consumption in this mode of 600 µW.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O3 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives
I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C1028 is packaged in high volume
industry standard packages.
Absolute maximum ratings
Parameter
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature under bias
DC output current
Symbol
V
t
P
D
T
stg
T
bias
I
out
Min
–0.5
–
–55
–10
–
Max
+7.0
1.0
+150
+85
20
Unit
V
W
o
C
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
out
D
in
Mode
Standby (I
SB
, I
SB1
)
Output Disable
Read
Write
Key: X = Don’t Care, L = LOW, H = HIGH
Recommended operating conditions
Parameter
Supply voltage
Input voltage
†
V min = –3.0V for pulse width less than t /2
IL
RC
(T
a
= 0°C to +70°C)
Symbol
V
CC
GND
V
IH
V
IL
Min
4.5
0.0
2.2
–0.5
†
Typ
5.0
0.0
–
–
Max
5.5
0.0
V
CC
+1
0.8
Unit
V
V
V
V
2
AS7C1028
AS7C1028L
DC operating characteristics
1
Parameter
Input leakage
current
Output
leakage current
Operating
power supply
current
Symbol Test Conditions
V
CC
= Max,
|
I
LI
|
V
in
= GND to V
CC
CE = V
IH
, V
CC
= Max,
|
I
LO
|
V
out
= GND to V
CC
I
CC
I
SB
CE = V
IL
,
f
=
f
max,
I
out
= 0 mA
CE = V
IH
,
f
=
f
max
L
L
-12
Min Max
–
–
–
–
–
–
–
–
–
2.4
1
1
130
125
50
45
5.0
1.0
0.4
–
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-15
Min Max
–
–
–
–
–
–
–
–
–
2.4
1
1
120
115
40
35
5.0
1.0
0.4
–
-20
Min Max
–
–
–
–
–
–
–
–
–
2.4
1
1
110
105
40
35
5.0
1.0
0.4
–
-25
Min Max
–
–
–
–
–
–
–
–
–
2.4
1
1
100
95
35
30
5.0
1.0
0.4
–
-35
Min Max
–
–
–
–
–
–
–
–
–
2.4
1
1
80
75
30
25
5.0
1.0
0.4
–
Unit
µA
µA
mA
mA
mA
mA
mA
mA
V
V
Standby
power supply
current
I
SB1
Output voltage
V
OL
V
OH
CE > V
CC
–0.2V,
f
= 0,
V
in
≤
0.2V
or
L
V
in
≥
V
CC
–0.2V
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Capacitance
2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE
I/O
(f = 1 MHz, T
a
= Room Temperature, V
CC
= 5V)
Test Conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
Key to switching waveforms
AAAAAAA
AAAAAAA
AAAAAAA
Rising input
AAAAAAA
AAAAAAA
AAAAAAA
Falling input
AAAAAAA
AAAAAAA
Undefined
AAAAAAA
output/don’t care
Read cycle
3,9
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold From address change
Chip enable to output in Low Z
Chip disable to output in High Z
Output enable to output in Low Z
Output disable to output in High Z
Chip enable to power up time
Chip Disable to power down time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
-12
Min Max
12
–
–
12
–
12
–
3
3
–
3
–
–
3
0
–
–
3
0
–
–
12
-15
Min Max
15
–
–
15
–
15
–
4
3
–
3
–
–
4
0
–
–
4
0
–
–
15
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-20
Min Max
20
–
–
20
–
20
–
5
3
–
3
–
–
5
0
–
–
5
0
–
–
20
-25
Min Max
25
–
–
25
–
25
–
6
3
–
3
–
–
6
0
–
–
6
0
–
–
25
-35
Min Max
35
–
–
35
–
35
–
8
3
–
3
–
–
8
0
–
–
8
0
–
–
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3
3
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
AS7C1028
AS7C1028L
Read waveform 1
3,6,7,9
t
RC
Address
t
AA
D
out
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
Address controlled
t
OH
Data Valid
Read waveform 2
3,6,8,9
t
RC1
CE
AAAAAAAAAAAAAAAAAAAAAAAAA
OE
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
CE controlled
t
OE
t
OLZ
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
ACE
D
out
t
CLZ
Supply
current
t
PU
t
OHZ
t
CHZ
Data Valid
t
PD
I
CC
I
SB
50%
50%
Write cycle
11
-12
Parameter
Symbol
Write cycle time
t
WC
Chip enable to write end
t
CW
Address setup to write end
t
AW
Address setup time
t
AS
Write pulse width
t
WP
Address hold from end of write t
AH
Data valid to write end
t
DW
Data hold time
t
DH
Write enable to output in High Z t
WZ
Output active from write end
t
OW
Min
12
10
10
0
8
0
8
0
–
3
Max
–
–
–
–
–
–
–
–
5
–
Min
15
10
10
0
9
0
9
0
–
3
-15
Max
–
–
–
–
–
–
–
–
5
–
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-20
Min
20
12
12
0
12
0
10
0
–
3
Max
–
–
–
–
–
–
–
–
5
–
Min
20
15
15
0
15
0
10
0
–
3
-25
Max
–
–
–
–
–
–
–
–
5
–
Min
30
20
20
0
17
0
15
0
–
3
-35
Max
–
–
–
–
–
–
–
–
5
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4, 5
4, 5
4, 5
4
AS7C1028
AS7C1028L
Write waveform 1
10,11
t
WC
t
AW
Address
WE
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
WE controlled
t
AH
t
WP
t
DW
Data Valid
t
WZ
t
OW
t
DH
t
AS
D
in
D
out
Write waveform 2
10,11
t
WC
t
AW
Address
t
AS
CE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
CE controlled
t
AH
t
CW
t
WP
t
WZ
t
DW
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
DH
D
in
D
out
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Data Valid
Data retention characteristics
Parameter
V
CC
for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Symbol
V
DR
I
CCDR
t
CDR
t
R
|
I
LI
|
Test Conditions
V
CC
= 2.0V
CE
≥
V
CC
–0.2V
V
in
≥
V
CC
–0.2V
or
V
in
≤
0.2V
Min
2.0
–
0
t
RC
–
Max
–
300
–
–
1
L version only
Unit
V
µA
ns
ns
µA
Data retention waveform
Data retention mode
V
CC
4.5V
t
CDR
CE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
IH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
L version only
V
DR
≥
2.0V
4.5V
t
R
V
DR
V
IH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
5
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