ACT
™
1 Series FPGAs
Fe atur es
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL
®
Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
De scrip tion
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Pr od uc t F a mi l y P r o fi le
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Logic Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
User I/Os (maximum)
Packages:
A1010B
A10V10B
1,200
3,000
30
12
295
147
22
13
112,000
57
44 PLCC
68 PLCC
A1020B
A10V20B
2,000
6,000
50
20
547
273
22
13
186,000
69
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE
®
antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
The user-definable I/Os are capable of driving at both TTL
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
44 PLCC
68 PLCC
84 PLCC
100 PQFP 100 PQFP
80 VQFP 80 VQFP
84 CPGA 84 CPGA
84 CQFP
75 MHz
55 MHz
75 MHz
55 MHz
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
Note:
See Product Plan on page 1-286 for package availability.
Th e De s i g ne r an d De s i gn e r
A dv a n t a ge ™ Sy s t em s
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft
®
Windows
™
and X Windows
™
graphical user
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap
™
VHDL optimization and synthesis tool
and the ACTgen
™
Macro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
April 1996
1-283
© 1996 Actel Corporation
The systems are available for 386/486/Pentium
™
PC and for
HP
™
and Sun
™
workstations and for running Viewlogic
®
,
Mentor Graphics
®
, Cadence
™
, OrCAD
™
, and Synopsys
design environments.
Figure 1 •
Partial View of an ACT 1 Device
AC T 1 De vice S truct ure
A partial view of an ACT 1 device (Figure 1) depicts four logic
modules and distributed horizontal and vertical interconnect
tracks. PLICE antifuses, located at intersections of the
horizontal and vertical tracks, connect logic module inputs
and outputs. During programming, these antifuses are
addressed and programmed to make the connections
required by the circuit application.
T he ACT 1 Logi c Modul e
The ACT 1 logic module is an 8-input, one-output logic circuit
chosen for the wide range of functions it implements and for
its efficient use of interconnect routing resources (Figure 2).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions, with
different combinations of active-low inputs. The logic module
can also implement a variety of D-latches, exclusivity
functions, AND-ORs, and OR-ANDs. No dedicated hardwired
latches or flip-flops are required in the array, since latches
and flip-flops may be constructed from logic modules
wherever needed in the application.
Figure 2 •
ACT 1 Logic Module
I/O Buff ers
Each I/O pin is available as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Outputs sink or
1-284
A C T
™
1 S eri es FP GA s
source 10 mA at TTL levels. See Electrical Specifications for
additional I/O buffer specifications.
De vice O rganizati on
A CT 1 Ar r a y Pe r fo r ma n ce
Temperature and Voltage Effects
ACT 1 devices consist of a matrix of logic modules arranged in
rows separated by wiring channels. This array is surrounded
by a ring of peripheral circuits including I/O buffers,
testability circuits, and diagnostic probe circuits providing
real-time diagnostic capability. Between rows of logic
modules are routing channels containing sets of segmented
metal tracks with PLICE antifuses. Each channel has 22
signal tracks. Vertical routing is permitted via 13 vertical
tracks per logic module column. The resulting network allows
arbitrary and flexible interconnections between logic
modules and I/O modules.
Probe P in
Worst-case delays for ACT 1 arrays are calculated in the same
manner as for masked array products. A typical delay
parameter is multiplied by a derating factor to account for
temperature, voltage, and processing effects. However, in an
ACT 1 array, temperature and voltage effects are less
dramatic than with masked devices. The electrical
characteristics of module interconnections on ACT 1 devices
remain constant over voltage and temperature fluctuations.
As a result, the total derating factor from typical to
worst-case for a standard speed ACT 1 array is only 1.19 to 1,
compared to 2 to 1 for a masked gate array.
Logic Module Size
ACT 1 devices have two independent diagnostic probe pins.
These pins allow the user to observe any two internal signals
by entering the appropriate net name in the diagnostic
software. Signals may be viewed on a logic analyzer using
Actel’s Actionprobe
®
diagnostic tools. The probe pins can
also be used as user-defined I/Os when debugging is finished.
Order ing Informati on
A1010
B
–
2
PL
84
Logic module size also affects performance. A mask
programmed gate array cell with four transistors usually
implements only one logic level. In the more complex logic
module (similar to the complexity of a gate array macro) of
an ACT 1 array, implementation of multiple logic levels
within a single module is possible. This eliminates interlevel
wiring and associated RC delays. The effect is termed “net
compression.”
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carriers
PQ = Plastic Quad Flatpacks
CQ = Ceramic Quad Flatpack
PG = Ceramic Pin Grid Array
VQ = Very Thin Quad Flatpack
Speed Grade
Blank = Standard Speed
–1
= Approximately 15% faster than Standard
–2
= Approximately 25% faster than Standard
–3
= Approximately 35% faster than Standard
Die Revision
B = 1.0 micron CMOS Process
Part Number
A1010
A1020
A10V10
A10V20
=
=
=
=
1200 Gates (5 V)
2000 Gates (5 V)
1200 Gates (3.3 V)
2000 Gates (3.3 V)
1-285
Pro du ct Plan
Speed Grade*
Std
A1010B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
A1020B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
84-pin Ceramic Quad Flatpack (CQ)
A10V10B Device
68-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
A10V20B Device
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
Applications: C
I
M
B
=
=
=
=
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–1
–2
–3
C
I
Application
M
B
Commercial Availability:
= Available
* Speed Grade: –1 = Approx. 15% faster than Standard
Industrial
P = Planned
–2 = Approx. 25% faster than Standard
Military
— = Not Planned
–3 = Approx. 35% faster than Standard
MIL-STD-883
De vic e R esou rces
User I/Os
Device
A1010B, A10V10B
A1020B, A10V20B
Logic Modules
295
547
Gates
1200
2000
44-pin
34
34
68-pin
57
57
80-pin
57
69
84-pin
57
69
100-pin
57
69
1-286
A C T
™
1 S eri es FP GA s
P in D escr i pti on
CLK
Clock (Input)
PRA
Probe A (Output)
TTL Clock input for global clock distribution network. The
Clock input is buffered prior to clocking the logic modules.
This pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect the
programmed design’s confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB
Probe B (Output)
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are automatically driven LOW by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/O. To provide Actionprobe capability, the MODE
pin should be terminated to GND through a 10K resistor so
that the MODE pin can be pulled high when required.
NC
No Connection
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect the
programmed design’s confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
V
CC
Supply Voltage
This pin is not connected to circuitry within the device.
Input HIGH supply voltage.
Ab solut e Maxim um R ati ngs
1
Free air temperature range
Symbol
V
CC
V
I
V
O
I
IO
T
STG
Parameter
DC Supply Voltage
2
Input Voltage
Output Voltage
I/O Sink/Source
Current
3
Storage Temperature
Limits
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
±
20
–65 to +150
Units
Volts
Volts
Volts
mA
°
C
R ec om m en d e d Op e r a t in g C o nd i t i ons
Parameter
Commercial
Industrial
Military
Units
Temperature
Range
1
Power Supply
Tolerance
0 to
+70
±
5
–40 to
+85
±
10
–55 to
+125
±
10
°
C
%V
CC
Note:
1. Ambient temperature (T
A
) used for commercial and industrial;
case temperature (T
C
) used for military.
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. V
PP
= V
CC
, except during device programming.
3. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than V
CC
+ 0.5 V or less than GND – 0.5 V, the internal protection
diode will be forward biased and can draw excessive current.
1-287
京公网安备 11010802033920号
EEWORLD
