MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MMSF5P02HD/D
Designer's
™
Data Sheet
Medium Power Surface Mount Products
MMSF5P02HD
Motorola Preferred Device
TMOS Single P-Channel
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process. These
miniature surface mount MOSFETs feature ultra low RDS(on) and true
logic level performance. They are capable of withstanding high energy in
the avalanche and commutation modes and the drain–to–source diode
has a very low reverse recovery time. MiniMOS devices are designed for
use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc–dc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
G
and offer additional safety margin against unexpected voltage transients.
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
•
Logic Level Gate Drive — Can Be Driven by Logic ICs
•
Miniature SO–8 Surface Mount Package — Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
IDSS Specified at Elevated Temperature
•
Avalanche Energy Specified
•
Mounting Information for SO–8 Package Provided
SINGLE TMOS
POWER MOSFET
8.7 AMPERES
20 VOLTS
RDS(on) = 0.03 OHM
™
D
CASE 751–05, Style 13
SO–8
S
Source
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
DEVICE MARKING
S5P02H
Device
MMSF5P02HDR2
ORDERING INFORMATION
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
4000 units
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MMSF5P02HD
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)
Negative sign for P–Channel devices omitted for clarity
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
1 inch SQ.
FR–4 or G–10 PCB
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Symbol
VDSS
VDGR
VGS
RTHJA
PD
ID
ID
IDM
RTHJA
PD
ID
ID
IDM
TJ, Tstg
EAS
1000
Max
20
20
±
8.0
50
2.5
20
8.7
7.0
43.5
80
1.56
12.5
6.9
5.5
35
– 55 to 150
Unit
V
V
V
°C/W
Watts
mW/°C
A
A
A
°C/W
Watts
mW/°C
A
A
A
°C
mJ
10 seconds
Minimum
FR–4 or G–10 PCB
10 seconds
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 19 Apk, L = 5.5 mH, RG = 25
W
)
(1) Repetitive rating; pulse width limited by maximum junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MMSF5P02HD
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
8.0 Vdc, VDS = 0)
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance
(VGS = 4.5 Vdc, ID = 6.4 Adc)
(VGS = 2.5 Vdc, ID = 5.1 Adc)
On–State Drain Current
(VDS
≤
5.0 V, VGS = 4.5 V)
(VDS
≤
5.0 V, VGS = 2.5 V)
Forward Transconductance (VDS = 9.0 Vdc, ID = 6.4 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
See Figure 8
6 4 Ad ,
(
(VDS = 6 0 Vd , ID = 6.4 Adc,
6.0 Vdc,
VGS = 4.5 Vdc) (1)
6.0 Vdc,
(VDD = 6 0 Vd ID = 1.0 Adc,
1 0 Ad
VGS = 4.5 Vdc,
4 5 Vdc
RG = 6.0
Ω)
( )
) (1)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage(1)
(IS = 2.5 Adc, VGS = 0 Vdc) (1)
(IS = 2.5 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
See Figure 15
(
(IS = 2 5 Ad , VGS = 0 Vdc,
2.5 Adc,
Vd ,
dIS/dt = 100 A/µs) (1)
Reverse Recovery Stored Charge
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
(4) Repetitive rating; pulse width limited by maximum junction temperature.
—
—
—
—
—
—
—
—
19
28
130
90
27.3
3.4
12
8.0
40
55
200
150
38
—
—
—
nC
ns
(VDS = 16 Vdc, VGS = 0 Vdc,
Vdc
Vdc
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
1400
925
370
1960
1300
520
pF
(1)
(Cpk
≥
2.0)
(1) (3)
VGS(th)
0.7
—
(Cpk
≥
2.0)
(1) (3)
RDS(on)
—
—
ID(on)
10
5.0
gFS
14
—
—
18
—
—
—
Mhos
22
35
30
45
A
0.9
2.6
1.4
—
Vdc
mV/°C
mΩ
(Cpk
≥
2.0)
(1) (3)
V(BR)DSS
20
—
IDSS
—
—
IGSS
—
—
—
—
1.0
25
100
nAdc
—
10
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
VSD
—
—
trr
ta
tb
QRR
—
—
—
—
0.77
0.6
95
35
60
0.151
1.2
—
180
—
—
—
Vdc
ns
µC
Motorola TMOS Power MOSFET Transistor Device Data
3
MMSF5P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
I D , DRAIN CURRENT (AMPS)
8.0
6.0
4.0
2.0
1.7 V
0
0
0.5
1.0
1.5
2.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0
1.0
1.5
2.0
2.5
3.0
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
4.5 V
2.7 V
3.1 V
3.7 V
2.1 V
VGS=
8
12
2.5 V
2.3 V
ID, DRAIN CURRENT (AMPS)
TJ = 25°C
10
8.0
6.0
100°C
4.0
2.0
25°C
TJ = –55°C
VDS
≥
10 V
1.9 V
Figure 1. On–Region Characteristics
R DS(on)
(W)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.06
ID = 6.4 A
TJ = 25°C
0.04
R DS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.06
TJ = 25°C
0.04
2.5 V
VGS = 4.5 V
0.02
0.02
0
0
2.0
4.0
6.0
8.0
10
VGS, GATE–TO–SOURCE (VOLTS)
0
0
2.0
4.0
6.0
8.0
10
12
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.0
VGS = 4.5 V
ID = 5.1 A
1.5
1000
VGS = 0 V
TJ = 125°C
IDSS , LEAKAGE (nA)
100
100°C
25°C
1.0
10
0.5
0
–50
1.0
–25
0
25
50
75
100
125
150
0
4.0
8.0
12
16
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
4
Motorola TMOS Power MOSFET Transistor Device Data
MMSF5P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
6000
Ciss
C, CAPACITANCE (pF)
Crss
TJ = 25°C
VGS = 0 V
4000
2000
Ciss
Coss
Crss
0
–10
VGS 0 VDS
10
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
5
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