74F64PC datasheet, PDF - EEWORLD Datasheet

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74F64PC: Description4-2-3-2-input AND-OR-invert gate; Categorylogic logic; File Size50KB，4 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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74F64PC Overview

4-2-3-2-input AND-OR-invert gate

74F64PC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, MS-001, DIP-14
Contacts	14
Reach Compliance Code	unknow
Is Samacsys	N
series	F/FAST
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.18 mm
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A
Number of functions	1
Number of entries	11
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	4.7 mA
Prop。Delay @ Nom-Su	7.5 ns
propagation delay (tpd)	7.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

74F64PC Related Products

	74F64PC	74F64	74F64SJ	74F64SC
Description	4-2-3-2-input AND-OR-invert gate	4-2-3-2-input AND-OR-invert gate	4-2-3-2-input AND-OR-invert gate	4-2-3-2-input AND-OR-invert gate
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	Fairchild	-	Fairchild	Fairchild
Parts packaging code	DIP	-	SOIC	SOIC
package instruction	0.300 INCH, PLASTIC, MS-001, DIP-14	-	SOP, SOP14,.3	SOP, SOP14,.25
Contacts	14	-	14	14
Reach Compliance Code	unknow	-	unknow	unknow
series	F/FAST	-	F/FAST	F/FAST
JESD-30 code	R-PDIP-T14	-	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e0	-	e0	e0
length	19.18 mm	-	10.2 mm	8.65 mm
Logic integrated circuit type	AND-OR-INVERT GATE	-	AND-OR-INVERT GATE	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A	-	0.02 A	0.02 A
Number of functions	1	-	1	1
Number of entries	11	-	11	11
Number of terminals	14	-	14	14
Maximum operating temperature	70 °C	-	70 °C	70 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	-	SOP	SOP
Encapsulate equivalent code	DIP14,.3	-	SOP14,.3	SOP14,.25
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	-	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	-	5 V	5 V
Maximum supply current (ICC)	4.7 mA	-	4.7 mA	4.7 mA
Prop。Delay @ Nom-Su	7.5 ns	-	7.5 ns	7.5 ns
propagation delay (tpd)	7.5 ns	-	7.5 ns	7.5 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Schmitt trigger	NO	-	NO	NO
Maximum seat height	5.08 mm	-	2.1 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	-	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	-	5 V	5 V
surface mount	NO	-	YES	YES
technology	TTL	-	TTL	TTL
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	GULL WING	GULL WING
Terminal pitch	2.54 mm	-	1.27 mm	1.27 mm
Terminal location	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	-	5.3 mm	3.9 mm
Base Number Matches	1	-	1	1

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