74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs
March 1988
Revised August 1999
74F646 • 74F646B • 74F648
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control G is Active LOW.
In the isolation mode (control G HIGH), A data may be
stored in the B register and/or B data may be stored in the
A register.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
74F648 has inverting data paths
s
74F646/74F646B have non-inverting data paths
s
74F646B is a faster version of the 74F646
s
3-STATE outputs
s
300 mil slim DIP
Ordering Code:
Order Number
74F646SC
74F646MSA
74F646SPC
74F646BSC
74F646BSPC
74F648SC
74F648SPC
Package Number
M24B
MSA24
N24C
M24B
N24C
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS009580
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74F646 • 74F646B • 74F648
Unit Loading/Fan Out
Pin Names
A
0
–A
7
B
0
–B
7
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
U.L.
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input I
IH
/I
IL
Output I
OH
/I
OL
70
µA/−650 µA
−12
mA/64 mA (48 mA)
70
µA/−650 µA
−12
mA/64 mA (48 mA)
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
Function Table
Inputs
G
H
H
H
L
L
L
L
L
L
L
L
DIR
X
X
X
H
H
H
H
L
L
L
L
CPAB CPBA SAB
H or L H or L
X
SBA
X
X
X
X
X
X
X
L
L
H
H
Output
Input
Input
Input
Input
Data I/O (Note 1)
A
0
–A
7
B
0
–B
7
Isolation
Clock A
n
Data into A Register
Clock B
n
Data into B Register
A
n
to B
n
—Real Time (Transparent Mode)
Output Clock A
n
Data into A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
—Real Time (Transparent Mode)
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
Data into B Register and Output to A
n
Function
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
H or L
H or L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Irrelevant
=
LOW-to-HIGH Transition
Note 1:
The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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74F646 • 74F646B • 74F648
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
−100
4.75
3.75
−0.6
70
−650
−225
500
135
150
150
10% V
CC
10% V
CC
2.0
0.55
5.0
7.0
0.5
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
mA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −15
mA (A
n
, B
n
)
I
OL
=
64 mA (A
n
, B
n
)
V
IN
=
2.7V (Non I/O Pins)
V
IN
=
7.0V (Non I/O Pins)
V
IN
=
5.5V (A
n
, B
n
)
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (Non I/O Pins)
V
OUT
=
2.7V (A
n
, B
n
)
V
OUT
=
0.5V (A
n
, B
n
)
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
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