INTEGRATED CIRCUITS
DATA SHEET
SAB9075H
Picture-in-Picture (PIP) controller
for NTSC
Preliminary specification
File under Integrated Circuits, IC02
February 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
FEATURES
Display
•
One or two live pictures can be displayed
simultaneously
•
Wide range of multi-Picture-In-Picture (PIP) modes
available
•
Six 6-bit Analog-to-Digital Converters (ADC) with
clamping circuit
•
Enhanced vertical resolution at most modes for live
pictures
•
Two Phase-Locked-Loops (PLL) with Voltage
Controlled Oscillator (VCO) to generate the line-locked
clocks
•
Three 7-bit Digital-to-Analog Converters (DAC)
•
4 : 1 : 1 data format
•
Data reduction factors 1 to 4, 1 to 9 and 1 to 16.
I
2
C-bus programmable
•
Different single, double and multi-PIP modes can be set
•
Several aspect ratios can be handled
•
Reduction factors can be set automatically and
manually
•
Selection of vertical filtering type
•
Freeze of live pictures
•
Single-PIP display position, four corners on-screen
•
Multi-PIP display position, left or right on-screen
•
Fine tuned display position, H (6-bit), V (6-bit)
•
Fine tuned acquisition area, H (4-bit), V (4-bit)
•
Channel-border and live PIP selectable
•
Eight main-border, sub-border, channel-border and
background colours selectable
•
Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
•
Several types of decoder input signals can be set
•
6-bit HUE and SAT signals (0 to 5 V) adjustable by
I
2
C-bus
•
Main and sub-audio mute controllable by I
2
C-bus.
GENERAL DESCRIPTION
SAB9075H
The SAB9075H is a picture-in-picture controller for the
NTSC environment in combination with the Integrated
NTSC decoder and sync processor TDA8315.
The device inserts one or two live video channels with
reduced sizes into a live video signal. All video signals are
expected to be analog baseband signals. The conversion
into the digital environment and back to the analog
environment is carried out on-chip. Internal clocks are
generated by two PLLs.
Due to the two PIP channels and a large external memory,
a wide range of PIP modes are offered. The emphasis is
put on double-PIP and multi-PIP modes. In combination
with the different border colours and some external
software the IC concept can be used as an excellent
channel selection tool.
Some of the I
2
C-bus registers are for controlling the
saturation and HUE of the colours. There are also outputs
for the mute function of main and sub-channel.
February 1995
2
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
SAB9075H
VERSION
SOT317-2
SAB9075H QFP100
(1)
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the
“Quality Reference Handbook”
(order number 9398 510 63011) are followed.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
tot
f
sys
f
loop
t
jitter
ς
Notes
1. Digital clocks are silent and analog bias current is zero.
2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see Section “PLLs and clock generation”.
PARAMETER
supply voltage
total supply current
system frequency
loop bandwidth frequency
short term stability time
damping factor
jitter during 1 line (64
µs)
note 1
note 2
CONDITIONS
all positive supply pins
tbf
−
4
−
−
MIN.
4.5
TYP.
5.0
220
27
−
−
0.7
MAX.
5.5
tbf
30
−
4
−
V
mA
MHz
kHz
ns
−
UNIT
February 1995
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white
to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
dbook, full pagewidth
February 1995
99
98
94
96
93
97
95
100
92
91
82
81
89
90
72
73
9
8
47
45
MY
MU
MV
MAI bias
MAV refT
MAV refB
CLAMP AND
A/D CONVERTER
ACQUISITION
MAIN
BLOCK DIAGRAM
Philips Semiconductors
Picture-in-Picture (PIP) controller for NTSC
SV SSD MVSSD
MAVSSD MAV SSA
SAVSSD
SAVSSA
RAS
WE
SAVDDA
SV DDD MV DDD
MAVDDD MAV DDA SAV DDD
CAS
DT
44
32
SC
DAO0 to 7
27
DAI0 to 7
AD0 to 8
DAV SSD
DAV SSA
DAV DDA
20
21
18
14
16
19
13
15
17
DAV DDD
11
10
36,39,40,38 29,31,35,33
41,46,37,34 26,25,30,28
48 to 56
DY
DU
DV
DAI bias
DAV refTU
DAV refTV
DAV refTY
D/A CONVERTER
AND BUFFER
SAB9075H
SY
SU
SV
SAI bias
SAV refT
SAV refB
87
83
85
88
86
84
MEMORY
CONTROL
4
CLAMP AND
A/D CONVERTER
ACQUISITION
SUB
DISPLAY
24
DBF
HUE
SAT
MMUTE
SMUTE
70
69
67
68
65
66
HUE AND SAT
D/A CONVERTERS
DISPLAY TIMING CONTROL
AND PLL BLOCK
I
2
C-BUS
63
64
75
MBE084
SCL
SDA
POR
A0
22
I
2
C VDD
42
V DDD
43
V SSS
71
SV sync
23
74
76
77
78
79
80
3
4
5
7
2
1
59
60
61
TM2
58
6
SPVDDD
SPI bias
MVsync
SPVSSD
MH sync
MPV SSD MPV SSA
TM0
SPVSSA
SPVDDA
SH sync
TM1
MPI bias
MPV DDD MPV DDA
MTCLK
TC
STCLK
Preliminary specification
SAB9075H
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
PINNING
SYMBOL
MPV
DDA
MPV
SSA
MH
sync
MPI
bias
MPV
SSD
MTCLK
MPV
DDD
MV
DDD
MV
SSD
DAV
DDD
DAV
SSD
n.c.
DAV
refTU
DU
DAV
refTV
DV
DAV
refTY
DY
DAI
bias
DAV
SSA
DAV
DDA
I
2
CV
DD
MV
sync
DBF
DAI5
DAI4
SC
DAI7
DAI0
DAI6
DAI1
DT
DAI3
DAO7
DAI2
DAO0
DAO6
DAO3
DAO1
DAO2
February 1995
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
I/O
I/O
I
I
I/O
I
I/O
I/O
I/O
I/O
I/O
−
I/O
O
I/O
O
I/O
O
I
I/O
I/O
I/O
I
O
I
I
O
I
I
I
I
O
I
O
I
O
O
O
O
O
TYPE
E030
E009
E027
E027
E009
HPP01
E030
E030
E009
E030
E009
−
E027
E027
E027
E027
E027
E027
E027
E009
E030
E030
HPP01
SPF20
HPP01
HPP01
OPF20
HPP01
HPP01
HPP01
HPP01
OPF20
HPP01
OPF20
HPP01
OPF20
OPF20
OPF20
OPF20
OPF20
5
DESCRIPTION
SAB9075H
analog positive power supply for PLL main-channel
analog negative power supply for PLL main-channel
horizontal synchronization for main-channel
analog bias reference current for PLL main-channel
digital negative power supply for PLL main-channel
test clock for main-channel
digital positive power supply for PLL main-channel
digital positive power supply for main-channel core
digital negative power supply for main-channel core
digital positive power supply for DACs
digital negative power supply for DACs
not connected
analog reference voltage for top U DAC
analog U output
analog reference voltage for top V DAC
analog V output
analog reference voltage for top Y DAC
analog Y output
analog bias reference current for DACs
analog negative power supply for DACs
analog positive power supply for DACs
positive supply for HUE and SAT decoders
vertical synchronization for main-channel
fast blanking control output signal
data bus input from memory; bit 5
data bus input from memory; bit 4
memory shift clock
data bus input from memory; bit 7
data bus input from memory; bit 0
data bus input from memory; bit 6
data bus input from memory; bit 1
memory data transfer; active LOW
data bus input from memory; bit 3
data bus output to memory; bit 7
data bus input from memory; bit 2
data bus output to memory; bit 0
data bus output to memory; bit 6
data bus output to memory; bit 3
data bus output to memory; bit 1
data bus output to memory; bit 2
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
