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AS7C32096A-12TCN

Description
Standard SRAM, 256KX8, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
Categorystorage    storage   
File Size163KB,9 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance
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AS7C32096A-12TCN Overview

Standard SRAM, 256KX8, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

AS7C32096A-12TCN Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts44
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time12 ns
JESD-30 codeR-PDSO-G44
JESD-609 codee3
length18.415 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)250
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width10.16 mm
Base Number Matches1
February 2005
Preliminary Information
®
AS7C32096A
3.3V 256K × 8 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 262,144 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
• ESD protection
2000 volts
• Latch-up current
200 mA
- 44-pin TSOP 2
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Pin arrangement
s
44-pin TSOP 2
Row decoder
262,144 × 8
Array
(2,097,152)
Sense amp
I/O1
I/O8
Column decoder
A10
A11
A12
A13
A14
A15
A16
A17
Control
Circuit
WE
OE
CE
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A17
A16
A15
A14
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A13
A12
A11
A10
NC
NC
NC
NC
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Industrial
Commercial
–10
10
4
180
170
8
–12
12
5
160
150
8
–15
15
6
140
130
8
–20
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
2/24/05, v. 1.0
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.

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