AS7C33128NTF18B-80TQCN datasheet, PDF

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AS7C33128NTF18B-80TQCN: DescriptionZBT SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100; Categorystorage storage; File Size429KB，19 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]; Environmental Compliance

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AS7C33128NTF18B-80TQCN Overview

ZBT SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33128NTF18B-80TQCN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	8 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	2359296 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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April 2005

AS7C33128NTF18B

3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD

Features

•

Organization: 131,072 words × 18 bits

NTD

™

architecture for efficient bus operation

Fast clock to data access: 7.5/8.0/10.0 ns

Fast OE access time: 3.5/4.0 ns

Fully synchronous operation

Flow-through mode

Asynchronous output enable control

Available in 100-pin TQFP package

•

Byte write enables

Clock enable for operation hold

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Self-timed write cycles

Interleaved or linear burst modes

Snooze mode for standby operation

Logic block diagram

A[16:0]

Address

burst logic

CLK

CE0

CE1

CE2

R/W

BWa

BWb

ADV / LD

LBO

CLK

Write delay

addr. registers

CLK

Control

logic

CLK

Write Buffer

128K x 18

SRAM

array

DQ [a,b]

Data

input

CLK

CEN

Output

buffer

DQ [a,b]

Selection guide

-75

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

8.5

7.5

260

110

-80

8.0

230

100

-10

200

Units

4/28/05, v 1.0

Alliance Semiconductor

P. 1 of 19

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