3UHOLPLQDU\#LQIRUPDWLRQ
®
$6:&64357//
6169#45;.ð;#,QWHOOLZDWWŒ#ORZ#SRZHU#&026#65$0
)HDWXUHV
• Intelliwatt active power reduction circuitry
• 2.7V to 3.6V operating range
• Organization: 131,072 words × 8 bits
• High speed
- 55/70/100 ns address access time
• Low power consumption
- Active: 126 mW max (55 ns cycle) at 3.6V
- Typical: <40mW (55 ns cycle)
- Standby: 180 µW
- Very low DC component in active power, 100µA max
• 1.5V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• JEDEC registered packaging
- 32-pin TSOP packag
- 48-ball 8mm × 6mm CSP BGA
• Class I, per Mil STD 883
• Latch-up current
≥
200 mA
• Industrial and commercial temperature available
• Other voltage versions available
- 1.65V to 1.95V (AS7C181024LL)
- 2.3V to 3.0V (AS7C251024LL)
65$0
65$0
65$0
65$0
/RJLF#EORFN#GLDJUDP
V
DD
V
SS
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
3LQ#DUUDQJHPHQW#+WRS#YLHZ,
A11
A9
A8
A13
WE
CE2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O4
I/O5
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
TSOP 8×20
I/O7
Row decoder
128K×8
Array
(1,048,576)
Sense amp
I/O0
Column decoder
Control logic,
Power reduction
WE
OE
CE1
CE2
48-CSP Ball-Grid-Array Package (shading indicates no ball)
1
2
3
4
5
6
A
A
0
A
1
CE2
A
3
A
6
A
8
B
I/O
4
A
2
WE
A
4
A
7
I/O
0
C
I/O
5
NC
A
5
I/O
1
D
V
SS
V
DD
E
V
DD
V
SS
F
I/O
6
NC
NC
I/O
2
G
I/O
7
OE
CE1
A
16
A
15
I/O
3
H
A
9
A
10
A
11
A
12
A
13
A
14
6HOHFWLRQ#JXLGH
7C31024LL-55
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum standby current
Intelliwatt™ is a trademark of Alliance Semiconductor Corporation.
A9
A10
A11
A12
A13
A14
A15
A16
7C31024LL-70
70
35
30
50
7C31024LL-100
100
50
25
50
Unit
ns
ns
mA
µA
55
25
35
50
','#440533490%1#;24<2<<
$//,$1&(#6(0,&21'8&725
438
Copyright ©1998 Alliance Semiconductor. All rights reserved.
$6:&64357//
®
3UHOLPLQDU\#LQIRUPDWLRQ
)XQFWLRQDO#GHVFULSWLRQ
The AS7C31024LL is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 131,072 words × 8
bits. It is designed for portable applications where fast data access, long battery life, and simple interfacing are desired.
65$0
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/100 ns with output enable access times (t
OE
) of 25/35/50 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory
systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. The AS7C31024LL is guaranteed not to exceed 180 µW power
,
consumption in standby mode. This device also returns data when V
DD
is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or wri te enable is
active, output drivers stay in high-impedance mode.
The device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides th e
smallest possible footprint. This 48-ball JEDEC registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.
/RZ#SRZHU#GHVLJQ
In the AS7C31024LL design, priority was placed on low power, while maintaining moderately high performance. To reduce standby an d
data retention current, a 6-transistor memory cell was utilized. Active power was reduced considerably over traditional designs by using
Intelliwatt™ power reduction circuitry. With Intelliwatt™, SRAM powers down unused circuits between access operations, resulting in
longer cycle times and lower duty cycles and providing incremental power savings. During periods of inactivity, Intelliwatt™ SRA M power
consumption can be as low as fully de-activated standby power, even though the chip is enabled. This power savings, both in acti ve and
inactive modes, results in longer battery life, and better system marketability. All chip inputs and outputs are TTL-compatible, and operation
is from a single 3.3V supply.
$EVROXWH#PD[LPXP#UDWLQJV
Parameter
Voltage on any input pin
Voltage on any I/O pin
Power dissipation
Storage temperature (plastic)
DC output current
Symbol
V
tIN
V
tI/O
P
D
T
stg
I
out
Min
–0.5
–0.5
–
–55
–
Max
+4.0
V
DD
+ 0.5
1.0
+150
20
Unit
V
V
W
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
7UXWK#WDEOH
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
H
L
X
Data
High Z
High Z
High Z
D
out
D
in
Mode
Standby (I
SB
, I
SB1
)
Standby (I
SB
, I
SB1
)
Output disable
Read
Write
Key: X = Don’t Care, L = LOW H = HIGH
,
439
$//,$1&(#6(0,&21'8&725
','#440533490%1#;24<2<<
$6:&64357//
®
3UHOLPLQDU\#LQIRUPDWLRQ
5HDG#F\FOH#
3,9
-55
Parameter
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
Min
55
–
–
–
3
3
–
3
–
0
–
Max
–
55
55
25
–
–
25
–
25
–
55
Min
70
–
–
–
3
3
–
3
–
0
–
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in Low Z
CE High to output in High Z
OE Low to output in Low Z
OE High to output in High Z
Power up time
Power down time
-70
Max
–
70
70
35
–
–
35
–
35
–
70
-100
Min
100
–
–
–
3
3
–
3
–
0
–
Max
–
100
100
50
–
–
50
–
50
–
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
3
3
Notes
65$0
.H\#WR#VZLWFKLQJ#ZDYHIRUPV
Rising input
Falling input
Undefined output/don’t care
$GGUHVV#FRQWUROOHG
t
RC
Address
t
AA
D
out
Data valid
t
OH
5HDG#ZDYHIRUP#4#
3,6,7,9,12
5HDG#ZDYHIRUP#5#
3,6,8,9,12
t
RC1
CE1
CE2
t
OE
OE
t
OLZ
t
ACE1, tACE2
D
out
t
CLZ1, tCLZ2
Current
supply
t
PU
50%
Data valid
t
PD
50%
t
OHZ
t
CHZ1, tCHZ2
&(4#DQG#&(5#FRQWUROOHG
I
CC
I
SB
43;
$//,$1&(#6(0,&21'8&725
','#440533490%1#;24<2<<
京公网安备 11010802033920号
EEWORLD
