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EDD5108AGTA-5CLI-E

Description
512M bits DDR SDRAM WTR (Wide Temperature Range)
Categorystorage    storage   
File Size476KB,52 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Environmental Compliance
Download Datasheet Parametric View All

EDD5108AGTA-5CLI-E Overview

512M bits DDR SDRAM WTR (Wide Temperature Range)

EDD5108AGTA-5CLI-E Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerELPIDA
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts66
Reach Compliance Codeunknow
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G66
JESD-609 codee6
length22.22 mm
memory density536870912 bi
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals66
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature50
width10.16 mm
PRELIMINARY DATA SHEET
512M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD5108AGTA-LI (64M words
×
8 bits)
EDD5116AGTA-LI (32M words
×
16 bits)
Specifications
Density: 512M bits
Organization
16M words
×
8 bits
×
4 banks (EDD5108AGTA)
8M words
×
16 bits
×
4 banks (EDD5116AGTA)
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
2.5V
±
0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8μs
Operating ambient temperature range
TA = –40°C to +85°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
·Wide temperature range
TA = –40°C to +85°C
Document No. E1304E10 (Ver. 1.0)
Date Published April 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2008
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