PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1208AATA (16M words
×
8 bits)
Specifications
•
Density: 128M bits
•
Organization
4M words
×
8 bits
×
4 banks
•
Package: 54-pin plastic TSOP (II)
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
3.3V
±
0.3V
•
Clock frequency: 133MHz (max.)
•
Four internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge operation for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
•
Operating ambient temperature range
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
EO
Features
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by DQM
Document No. E0660E20 (Ver. 2.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005
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A0 to A11
BA0, BA1
/CS
/RAS
/CAS
/WE
DQM
DQ0 to DQ7
(Top view)
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
CKE
CLK
VDD
VSS
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
uc
Power for DQ circuit
Ground for DQ circuit
No connection
VDDQ
VSSQ
NC
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EDS1208AATA
Ordering Information
Part number
EDS1208AATA-75-E*
Supply
voltage
3.3V
Organization
(words
×
bits) Internal Banks
16M
×
8
4
Clock frequency
MHz (max.)
133
/CAS latency
3
Package
54-pin plastic
TSOP (II)
Note: 100MHz operation at /CAS latency = 2.
Part Number
E D S 12 08 A A TA - 75 - E
Elpida Memory
Type
Environment Code
E: Lead Free
EO
D: Monolithic Device
Product Family
S: SDRAM
Density / Bank
12: 128M/4-bank
Organization
08: x8
Speed
75: 133MHz/CL3
100MHz/CL2
Power Supply, Interface
A: 3.3V, LVTTL
Die Rev.
Preliminary Data Sheet E0660E20 (Ver. 2.0)
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Package
TA: TSOP (II)
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EDS1208AATA
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................20
Mode Register Configuration.......................................................................................................................21
Power-up sequence.....................................................................................................................................23
Operation of the SDRAM.............................................................................................................................24
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
EO
Preliminary Data Sheet E0660E20 (Ver. 2.0)
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EDS1208AATA
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to VDD + 0.5 (≤ 4.6 (max.))
–0.5 to +4.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
EO
Parameter
Supply voltage
Input high voltage
Input low voltage
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
min.
3.0
0
2.0
–0.3
max.
3.6
0
VDD + 0.3
0.8
Unit
V
V
V
V
Notes
1
2
3
4
L
VIL
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width
≤
5ns).
VIL (min.) = VSS – 1.5V (pulse width
≤
5ns).
Preliminary Data Sheet E0660E20 (Ver. 2.0)
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EDS1208AATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power down
Standby current in non power down
(input signal stable)
Active standby current in power down
Active standby current in power down
(input signal stable)
Active standby current in non power down
Active standby current in non power down
(input signal stable)
Burst operating current
Refresh current
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
IDD6
Grade
max.
100
3
2
20
9
4
3
40
25
120
220
1.5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
EO
Self refresh current
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0660E20 (Ver. 2.0)
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