K5A3x40YT(B)C
Multi-Chip Package MEMORY
Preliminary
MCP MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
FEATURES
•
Power Supply voltage : 2.7V to 3.3V
•
Organization
- Flash : 4,194,304 x 8 / 2,097,152 x 16 bit
- SRAM : 524,288 x 8 / 262,144 x 16 bit
•
Access Time (@2.7V)
- Flash : 70 ns, SRAM : 55 ns
•
Power Consumption (typical value)
- Flash Read Current : 14 mA (@5MHz)
Program/Erase Current : 15 mA
Standby mode/Autosleep mode : 5
µA
Read while Program or Read while Erase : 25 mA
- SRAM Operating Current : 20 mA
Standby Current : 0.5
µA
•
Secode(Security Code) Block : Extra 64KB Block (Flash)
•
Block Group Protection / Unprotection (Flash)
•
Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb
•
Flash Endurance : 100,000 Program/Erase Cycles Minimum
•
SRAM Data Retention : 1.5 V (min.)
•
Industrial Temperature : -40°C ~ 85°C
•
Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch
1.2mm(max.) Thickness
GENERAL DESCRIPTION
The K5A3x40YT(B)C featuring single 3.0V power supply is a
Multi Chip Package Memory which combines 32Mbit Dual Bank
Flash and 4Mbit fCMOS SRAM.
The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit
and 4Mbit SRAM is organized as 512K x8 or 256K x16 bit. The
memory architecture of flash memory is designed to divide its
memory arrays into 71 blocks and this provides highly flexible
erase and program capability. This device is capable of reading
data from one bank while programming or erasing in the other
bank with dual bank organization.
The Flash memory performs a program operation in units of 8 bits
(Byte) or 16 bits (Word) and erases in units of a block. Single or
multiple blocks can be erased. The block erase operation is com-
pleted for typically 0.7sec.
The 4Mbit SRAM supports low data retention voltage for battery
backup operation with low data retention current.
The K5A3x40YT(B)C is suitable for the memory of mobile com-
munication system to reduce mount area. This device is available
in 69-ball TBGA Type package.
BALL CONFIGURATION
BALL DESCRIPTION
Ball Name
A
0
to A
17
Description
Address Input Balls (Common)
Address Input Balls (Flash Memory)
Data Input/Output Balls (Common)
Hardware Reset (Flash Memory)
Write Protection / Acceleration Program
(Flash Memory)
Power Supply (SRAM)
Power Supply (Flash Memory)
Ground (Common)
Upper Byte Enable (SRAM)
Lower Byte Enable (SRAM)
BYTE
S
Control (SRAM)
BYTE
F
Control (Flash Memory)
Address Inputs (SRAM)
Chip Enable (Flash Memory)
Chip Enable (SRAM Low Active)
Chip Enable (SRAM High Active)
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
No Connection
1
A
B
C
D
E
F
G
H
J
K
N.C
N.C
N.C
2
3
4
5
N.C
6
7
8
9
10
A-1, A
18
to A
20
DQ
0
to DQ
15
N.C
N.C
RESET
WP/ACC
N.C
A7
LB
WP/
ACC
WE
A8
A11
A3
A6
UB
RESET CS2
S
A19
A12
A15
Vcc
S
Vcc
F
Vss
UB
LB
A2
A5
A18
RY/BY
A20
A9
A13
N.C
A1
A4
A17
A10
A14
N.C
N.C
N.C
A0
Vss
DQ1
DQ6
SA
A16
N.C
BYTE
S
DQ3
DQ4
DQ13
DQ15 BYTE
F
/A-1
DQ7
Vss
CE
F
OE
DQ9
BYTE
F
SA
CE
F
CS1
S
DQ0
DQ10
Vcc
F
Vcc
S
DQ12
DQ8
DQ2
DQ11
BYTE
S
DQ5
DQ14
CS1
S
CS2
S
N.C
N.C
N.C
WE
OE
69 Ball TBGA , 0.8mm Pitch
RY/BY
N.C
Top View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
-2-
Revision 0.0
November 2002
Switching Power Supply Study Group
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