or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1026_14.1
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today’s system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the
sysHSI Block.
Electrically Erasable CMOS (E
2
CMOS) memory cells provide the ispXPGA family with non-volatile capability.
These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-
tions. This capability also means that expensive external configuration memories are not required and that designs
can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if
desired. Both the SRAM and E
2
CMOS cells can be programmed and verified through the IEEE 1532 industry stan-
dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.
The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M system
gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-
ing easy integration into the overall system.
System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-
ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization
(SERDES).
The ispLEVER™ design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-
thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these
common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor
planning and the management of other constraints within the device. The tool also provides outputs to common
timing analysis tools for timing analysis.
To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the
ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using
pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,
and memory controllers.
Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-
ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.
Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly
used by logic designers.
Table 2. ispXPGA Speed Performance for Typical Building Blocks
Function
8:1 Asynch MUX
1:32 Asynch Demultiplexer
8 x 8 2-LL Pipelined Multiplier
32-bit Up/Down Counter
32-bit Shift Register
Performance
150 MHz
125 MHz
225 MHz
290 MHz
360 MHz
2
Lattice Semiconductor
ispXPGA Family Data Sheet
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can
be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
3
Lattice Semiconductor
Figure 1. ispXPGA Block Diagram
ispXPGA Family Data Sheet
PFU
PIC
sysMEM Block
sysCLOCK PLL
sysHSI Block
sysIO Buffer
Programmable Function Unit
The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are
arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of
four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-
erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of
the function capabilities of the PFU.
There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-
trol logic from which six control signals are derived for the PFU.
Table 3. Function Capability of ispXPGA PFU
Function
Look-up table
Wide logic functions
Multiplexing
Arithmetic logic
Single-port RAM
Double-port RAM
Shift register
LUT-4, LUT-5, LUT-6
Up to 20 input logic functions
2:1, 4:1, 8:1
Dedicated carry chain and booth multiplication logic
16X1, 16X2, 16X4, 32X1, 32X2, 64X1
16X1, 16X2, 32X1
8-bit shift registers (up to 32-bit shift capability)
Five skills required for RF test engineers
RF Test Engineers are an integral part of every manufacturing environment as well as the development team of advanced RF products and projects.Some people sa...
In addition to the conventional I2C interface monochrome OLED screen, there is also a color OLED screen based on the SPI interface, which makes it more expressive and can display color pictures.
There...
[i=s]This post was last edited by qwqwqw2088 on 2022-10-25 09:56[/i]In recent years, a series of outdoor sports such as camping, picnics, and wild fishing have quickly become popular. From a niche hob...
[size=4][color=#000000]Phenomenon: After a wireless network card is powered on, without any operation, the four PAs will emit a lot of heat, and the surface temperature of the PA is very high and hot....
What is the function of the cross-connection of the five tubes in the middle of this comparator? The test shows that it is a falling edge trigger. Where is the falling edge trigger? Please help. It wo...
In the design process of microcontroller (MCU) system, developers often need to develop applications with battery life close to the service life of the final product. For example: when designing porta...[Details]
The STM8 microcontroller has its own unique terminal system What is an interrupt? What are interrupt sources? An event or source that causes an interrupt is called an interrupt source. The STM8S208...[Details]
This article introduces in detail the basic knowledge of serial port, ISP download of 51 single-chip microcomputer, etc. Those who have already learned single-chip microcomputer can also take a look...[Details]
Power supply designers often face conflicting requirements. On the one hand, they need to reduce size and cost, and on the other hand, they need to provide more functions and increase output power. D...[Details]
Recently, Suzhou Guoxin Technology Co., Ltd. (hereinafter referred to as "Guoxin Technology"), the "first domestic CPU stock", was listed on the Science and Technology Innovation Board with an issue ...[Details]
Recently, Velodyne, a lidar supplier, released its Q4 and full-year financial report for 2021. Data showed that in Q4 2021, Velodyne's revenue was US$17.5 million, up 34.3% from Q3 and roughly the sa...[Details]
Level characteristics The microcontroller is a digital integrated chip that uses a digital circuit. In a digital circuit, there are only two levels: high level (5V) and low level (0V). The input and ...[Details]
Dagang NeXchange Bhd (DNeX) announced that it has signed a takeover offer with Khazanah Nasional Berhad (Khazanah) to acquire SilTerra Malaysia Sdn Bhd, a Malaysian 8-inch wafer foundry. DNeX announc...[Details]
Lingsheng Technology held a "Lingsheng Housewarming Celebration" event on the first floor of the company's new office building in Zhangjiang Startup World. Guests including He Dajun, Deputy General M...[Details]
Following Apple, Samsung also launched its own repair service Business Code April 2 (Shao Feng) reported that after Apple launched its self-repair service, the right to repair movement has once again...[Details]
After overcoming the controversy over screen defects, Galaxy Fold has been sold in South Korea. Many consumers have received the physical phones. As media and consumers continue to upload reviews, th...[Details]
How does Tesla achieve such a long battery life? The battery and motor remain unchanged, and the range of Tesla's Model Y is slightly reduced compared to Model 3. Even so, the latest data release...[Details]
introduction Compared with AC motors, DC motors have the characteristics of excellent speed regulation, rapid starting, large starting torque, and strong load carrying capacity. Therefore, they a...[Details]
According to foreign media reports, TSMC, which is promoting mass production of 3nm process technology with a considerable yield rate, is also promoting more advanced 2nm and 1nm process technology. ...[Details]
The electronic control system of an electronically controlled engine is a highly integrated electronic control system that controls the operation of the engine through electronic signals to improve...[Details]
Test/Measurement
京公网安备 11010802033920号
EEWORLD
