ACE24C128/256
Technology
Description
Two-wire Serial EEPROM
The ACE24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read-only
memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up
to 8 devices to share a common two-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
Features
Low Operation Voltage: Vcc = 1.7V to 5.5V
Internally Organized: 16,384 x 8(128K), 32,768 x 8(256K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility
Write Protect Pin for Hardware Data Protection
64-byte Page Write Modes (Partial Page Writes are Allowed)
Self-timed Write Cycle (5 ms max)
High-reliability - Endurance: 1,000,000 Write Cycles
- Data Retention: 100 Years
PDIP-8,SOP-8,TSSOP-8 ROHS compliant Packages
Wafer Sales: available in inked wafer Form
Absolute Maximum Ratings
Operating Temperature
Storage Temperature
Voltage on Any Pin with Respect to Ground
Maximum Operating Voltage
DC Output Current
-55℃ to +125℃
-65℃ to +150℃
-1.0V to +7.0V
6.25V
5.0 mA
*Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
VER 1.2
1
ACE24C128/256
Technology
Packaging Type
Two-wire Serial EEPROM
Pin Configurations
Pin Name
A0~A2
SDA
SCL
WP
VCC
GND
Function
Device Address Inputs
Serial Data Input / Output
Serial Clock Input
Write Protect
Power Supply
Ground
VER 1.2
2
ACE24C128/256
Technology
Block Diagram
Two-wire Serial EEPROM
Figure 1
VER 1.2
3
ACE24C128/256
Technology
Ordering information
Selection Guide
ACE24C128/256 XX
+
X H
Halogen-free
U : Tube
T : Tape and Reel
Pb - free
DP : PDIP-8
FM : SOP-8
TM : TSSOP-8
Two-wire Serial EEPROM
Serial Clock (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
Serial Data (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device/Page Addresses (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for
hardware compatibility with other ACE24CXXX/ACE24CXXX devices. When the pins are hardwired,
as many as eight 128K/256K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).If the pins are left floating, the A2, A1 and A0
pins will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane is <
3pF, if coupling is > 3pF recommends connecting the address pins to GND.
Write Protect (WP):
The ACE24C128/256 has a Write Provides hardware data protection. The WP pin allows normal write
operations when connected to ground (GND). When the Write Protect pin is connected to Vcc. All write
operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled is
< 3pF , if coupling is > 3pF, recommends connecting the pins to GND. Switching WP to Vcc prior to a
write operation creates a software write protected function.
Write Protect Description
WP Pin Status
WP=V
CC
WP=GND
Part of the Array Protected
ACE24C128
Full (128K) Memory
ACE24C256
Full (256K) Memory
Normal Read/Write Operations
VER 1.2
4
ACE24C128/256
Technology
Memory Organization
Two-wire Serial EEPROM
ACE24C128, 128K Serial EEPROM:
Internally organized with 256 pages of 64 bytes each, Random word addressing requires a 14-bit data
word address.
ACE24C256, 256K Serial EEPROM:
Internally organized with 512 pages of 64 bytes each, Random word addressing requires a 15-bit data
word address.
Pin Capacitance
Applicable over recommended operating range from: T
A
= 25℃, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O 1
C
IN 1
Test Condition
Input / Output Capacitance
Input Capacitance
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: T
A
= -40℃ to +85℃, V
CC
= +1.7V to +5.5V, (unless otherwise noted).
Symbol
V
CC
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
OL2
V
OL1
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Output Low Level 2
Output Low Level 1
Test Condition
Min
1.7
Typ
Max
5.5
Units
V
mA
mA
µA
µA
µA
µA
V
V
V
V
V
CC
= 5V, Read at 400KHz
V
CC
= 5V, Write at 400KHz
V
CC
= 1.7V, V
IN
= V
CC
/ V
SS
V
CC
= 5.5V, V
IN
= V
CC
/ V
SS
V
IN
= V
CC
/V
SS
V
OUT
= V
CC
/ V
SS
-0.6
V
CC
x0.7
V
CC
= 3.0V, I
OL
= 2.1 mA
V
CC
= 1.7V, I
OL
= 0.15 mA
0.4
2.0
1.0
3.0
1.0
6.0
0.10
0.05
3.0
3.0
V
CC
x0.3
V
CC
+0.5
0.4
0.2
Note: 1. V
IL
min and V
IH
max are reference only and are not tested.
VER 1.2
5
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