Figure 3. 48-pin TSOP I (512 K × 16/1 M × 8) (Top View)
[1, 3]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
Range
V
CC
Range (V)
Min
CY62157EV30LL
Industrial/Auto-A
Auto-E
2.2
2.2
Typ
[4]
3.0
3.0
Max
3.6
3.6
45
55
Speed
(ns)
Operating I
CC
, (mA)
f = 1 MHz
Typ
[4]
1.8
1.8
Max
3
4
f = f
max
Typ
[4]
18
18
Max
25
35
Standby, I
SB2
(A)
Typ
[4]
2
2
Max
8
30
Notes
1. NC pins are not connected on the die.
2. The 44-pin TSOP II package has only one chip enable (CE) pin.
3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512 K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1 M × 8
SRAM by tying the BYTE signal LOW. In the 1 M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O
8
to I/O
14
pins are not used (NC).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document #: 38-05445 Rev. *I
Page 3 of 21
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CY62157EV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................. –65 °C to + 150 °C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Supply Voltage to Ground
Potential .............................–0.3 V to 3.9 V (V
CCmax
+ 0.3 V)
DC Voltage Applied to Outputs
in High Z State
[5, 6]
............–0.3 V to 3.9 V (V
CCmax
+ 0.3 V)
DC Input Voltage
[5, 6]
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ........................................> 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current ...................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
[7]
CY62157EV30LL Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V
Auto-A
Auto-E
–40 °C to +125 °C
........ –0.3 V to 3.9 V (V
CC max
+ 0.3 V)
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
V
CC
operating supply
current
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70 V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
GND < V
I
< V
CC
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
Output leakage current GND < V
O
< V
CC
, Output Disabled
45 ns (Industrial/
Auto-A)
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
–
Typ
[8]
–
–
–
–
–
–
–
–
–
–
18
1.8
2
Max
–
–
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
+1
25
3
8
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–4
–4
–
–
–
55 ns (Auto-E)
Min
Typ
[8]
–
–
–
–
–
–
–
–
–
–
18
1.8
2
Max
–
–
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+4
+4
35
4
30
mA
A
V
V
V
V
V
V
V
V
A
A
Unit
I
SB1 [9]
Automatic CE power CE
1
> V
CC
0.2
V or CE
2
< 0.2 V
down current — CMOS or (BHE and BLE) > V
CC
– 0.2 V,
inputs
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60 V
Automatic CE power CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V
down current — CMOS or (BHE and BLE) > V
CC
– 0.2 V,
inputs
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
I
SB2 [9]
–
2
8
–
2
30
A
Notes
5. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100
s
ramp time from 0 to V
cc
(min) and 200
s
wait time after V
CC
stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
9. Chip enables (CE
1
and CE
2
), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other
inputs can be left floating.
Document #: 38-05445 Rev. *I
Page 4 of 21
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CY62157EV30 MoBL
®
Capacitance
Parameter
[10]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[10]
JA
JC
Description
Thermal resistance
(Junction to Ambient)
Thermal resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5
inch, two-layer printed circuit
board
48-ball BGA
72
8.86
44-pin TSOP I 44-pin TSOP II Unit
74.88
8.6
76.88
13.52
C/W
C/W
Figure 4. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
10%
GND
R2 Rise Time = 1 V/ns
Equivalent to:
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
30 pF
INCLUDING
JIG AND
SCOPE
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
3.0 V
1103
1554
645
1.75
Unit
V
Parameters
R1
R2
R
TH
V
TH
2.5 V
16667
15385
8000
1.20
Note
10. Tested initially and after any design or process changes that may affect these parameters.
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