FBL2031BB datasheet, PDF - EEWORLD Datasheet

FBL2031BB: DescriptionRegistered Bus Transceiver, 1-Func, 9-Bit, Inverted Output, BICMOS, PQFP52,; Categorylogic logic; File Size117KB，16 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

Download Datasheet Parametric View All

FBL2031BB Overview

Registered Bus Transceiver, 1-Func, 9-Bit, Inverted Output, BICMOS, PQFP52,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	QFP, QFP52,.52SQ
Reach Compliance Code	unknown
Is Samacsys	N
Control type	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL
JESD-30 code	S-PQFP-G52
JESD-609 code	e0
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.1 A
Number of digits	9
Number of functions	1
Number of terminals	52
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-COLLECTOR/3-STATE
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP52,.52SQ
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Maximum supply current (ICC)	32 mA
Prop。Delay @ Nom-Sup	8.4 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
translate	BTL & TTL
Trigger type	POSITIVE EDGE
Base Number Matches	1

EEWORLD University ---- RISC-V Processor Design Series: RISC-V Processor Design Series : https://training.eeworld.com.cn/course/5612This video is a series of courses, mainly using the open source Hummingbird E203 processor as an example to explain RISC-V p...; 小白two FPGA/CPLD

[NUCLEO-L552ZE Review] +RT-Thread Porting: I attended the annual RT-Thread Developer Conference in Shenzhen last weekend, and this week I plan to port an operating system to the NUCLEO-L552ZE development board. Conclusion first: System transpl...; Rimas stm32/stm8

Single source shortest path - Dijkstara algorithm: The basic idea of the algorithm is: find the vertex closest to the source point each time, then expand with this vertex as the center, and finally get the shortest path from the source point to all ot...; 灞波儿奔 Microcontroller MCU

Synopsys' latest IP resource recommendations - artificial intelligence, automotive, and high-performance computing: The IP resources shared by Synopsys in this issue include the latest technical solutions and cutting-edge technology interpretations in three major industries.AI AI+ML, let chip verification end this ...; arui1999 Integrated technical exchanges

AD PCB ad cannot be selected after copper coating, it is not a problem of which layer: I can't select the copper part after the ad is covered. I created it on the top layer and immediately selected it. I tried it on other layers, but they can't be selected after they are created. I can ...; 示范法 PCB Design

About fatalerror in Modelsim simulation: ISE feels pretty good. Modelsim just prompts this. Is there any brother who can teach me?...; li617296559 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components