MK1709S datasheet, PDF - EEWORLD Datasheet

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MK1709S: DescriptionPLL Based Clock Driver, 1709 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8; Categorylogic logic; File Size167KB，9 Pages; ManufacturerIDT (Integrated Device Technology)

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MK1709S Overview

PLL Based Clock Driver, 1709 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8

MK1709S Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	0.150 INCH, SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
series	1709
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	1
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
minfmax	167 MHz
Base Number Matches	1

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DATASHEET

LOW EMI CLOCK GENERATOR

Description

The MK1709 generates a low EMI output clock from a clock

input. The part is designed to dither the LCD interface clock

for flat panel graphics controllers. The device uses IDT’s

proprietary mix of analog and digital Phase Locked Loop

(PLL) technology to spread the frequency spectrum of the

output, thereby reducing the frequency amplitude peaks by

several dB.

The MK1709 offers centered spread from a high speed

clock input. Refer to the MK1714-01/02 for a crystal input

and the widest selection of input frequencies and

multipliers.

IDT offers many other clocks for computers and computer

peripherals. Consult us when you need to remove crystals

and oscillators from your board.

MK1709

Features

•

Packaged in 8-pin SOIC (MK1709S) and in 8-pin TSSOP

(MK1709AG)

•

Available in lead (Pb) free package

Provides a spread spectrum output clock

Supports flat panel controllers

Guaranteed to +85° C operation

Accepts a clock input, provides same frequency dithered

output

•

Good for all VGA modes from 40 to 167 MHz

•

Peak reduction by 7dB - 14dB typical on 3rd - 19th odd

harmonics

•

Low EMI feature can be disabled

Includes power-down

Operating voltage of 3.3 V

Advanced, low-power CMOS process

NOTE: EOL for non-green parts to occur on 5/13/10

per PDN U-09-01

Block Diagram

VDD

Low EMI Enable

PLL Clock

Synthesis

and Spread

Spectrum

Circuitry

Input

Buffer

Clock Out

ICLK

GND

IDT™ VBLOW

EMI CLOCK GENERATOR

MK1709

REV K 121809

MK1709S Related Products

	MK1709S	MK1709AG	MK1709STR
Description	PLL Based Clock Driver, 1709 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8	PLL Based Clock Driver, 1709 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.173 INCH, TSSOP-8	PLL Based Clock Driver, 1709 Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8
Is it lead-free?	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SOIC	SOIC	SOIC
package instruction	0.150 INCH, SOIC-8	TSSOP, TSSOP8,.25	0.150 INCH, SOIC-8
Contacts	8	8	8
Reach Compliance Code	not_compliant	not_compliant	not_compliant
series	1709	1709	1709
Input adjustment	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0	e0
length	4.9 mm	4.4 mm	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A	0.012 A	0.012 A
Number of functions	1	1	1
Number of terminals	8	8	8
Actual output times	1	1	1
Maximum operating temperature	85 °C	85 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP
Encapsulate equivalent code	SOP8,.25	TSSOP8,.25	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	240
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.2 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30
width	3.9 mm	3 mm	3.9 mm
minfmax	167 MHz	165 MHz	167 MHz
Base Number Matches	1	1	-

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