LXT9782BC datasheet, PDF - EEWORLD Datasheet

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LXT9782BC: DescriptionEthernet Transceiver, PBGA272, PLASTIC, BGA-272; CategoryWireless rf/communication Telecom circuit; File Size1MB，78 Pages; ManufacturerInphi Corporation

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LXT9782BC Overview

Ethernet Transceiver, PBGA272, PLASTIC, BGA-272

LXT9782BC Parametric

Parameter Name	Attribute value
Maker	Inphi Corporation
package instruction	BGA,
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B272
length	27 mm
Number of functions	1
Number of terminals	272
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2.32 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	27 mm
Base Number Matches	1

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LXT9762/9782

Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII

Datasheet

General Description

The LXT9782 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical

layer applications at both 10 and 100 Mbps. The LXT9762 offers the same features and

functionality in a six-port device. This data sheet uses the singular designation “LXT97x2” to

refer to both devices.

The LXT97x2 interfaces multiple Serial Media Independent Interface (SMII) compliant

controllers to 10BASE-T and/or 100BASE-TX media.

All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for

a 10/100BASE-TX or 100BASE-FX connection.

The LXT97x2 provides three discrete LED drivers for each port, and eight global serial LED

outputs. It supports both half- and full-duplex operation at 10 and 100 Mbps and requires only a

single 3.3V power supply.

Application

100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.

Product Features

Multiple independent IEEE 802.3-

compliant 10/100 ports with integrated

filters

Proprietary Optimal Signal Processing

(OSP™) design improves SNR by 3 dB

over ideal analog filters

Robust baseline wander correction for

improved 100BASE-TX performance

100BASE-FX fiber-optic capability on all

ports

Supports both auto-negotiation and legacy

systems without auto-negotiation capability

JTAG boundary scan

Multiple Serial MII (SMII) ports for

independent PHY port operation

Configurable via MDIO port or external

control pins

Maskable interrupts

Very low power consumption

(400 mW per port, typical)

3.3V operation

208-pin PQFP and 272-lead BGA

0-70

C ambient temperature range

As of January 15, 2001, this document replaces the Level One document

LXT9762/9782 — Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII.

Order Number: 249039-001

January 2001

Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782

Contents

1.0

2.0

Preliminary Pin Assignments and Signal Descriptions

...........................10

Functional Description

...........................................................................................20

2.1

Introduction..........................................................................................................20

2.1.1 OSP™ Architecture ................................................................................20

2.1.2 Comprehensive Functionality .................................................................20

Interface Descriptions..........................................................................................21

2.2.1 10/100 Network Interface .......................................................................21

2.2.2 SMII Data Interface ................................................................................22

2.2.3 Configuration Management Interface .....................................................22

Operating Requirements .....................................................................................25

2.3.1 Power Requirements..............................................................................25

2.3.2 Clock Requirements ...............................................................................25

Initialization..........................................................................................................25

2.4.1 Hardware Configuration Settings ...........................................................26

2.4.2 Reset ......................................................................................................27

2.4.3 Power-Down Mode.................................................................................28

Link Establishment ..............................................................................................28

2.5.1 Auto-Negotiation.....................................................................................28

2.5.2 Parallel Detection ...................................................................................29

Serial MII Operation ............................................................................................29

2.6.1 Reference Clock.....................................................................................31

2.6.2 SYNC Pulse ...........................................................................................31

2.6.3 Transmit Data Stream ............................................................................31

2.6.4 Receive Data Stream .............................................................................32

2.6.5 Loopback................................................................................................33

2.6.6 Collision..................................................................................................33

100 Mbps Operation............................................................................................34

2.7.1 100BASE-X Network Operations ...........................................................34

2.7.2 .100BASE-X Protocol Sublayer Operations ...........................................35

10 Mbps Operation..............................................................................................39

2.8.1 10T Preamble Handling..........................................................................40

2.8.2 10T Dribble Bits......................................................................................40

2.8.3 10T Link Test..........................................................................................40

2.8.4 10T Jabber .............................................................................................40

Monitoring Operations .........................................................................................40

2.9.1 Serial LED Functions..............................................................................40

2.9.2 Per-Port LED Driver Functions ...............................................................42

2.9.3 Monitoring Auto-Negotiation...................................................................43

2.9.4 Using the Quick Status Register ............................................................44

Boundary Scan (JTAG1149.1) Functions............................................................44

2.10.1 Boundary Scan Interface........................................................................44

2.10.2 State Machine ........................................................................................45

2.10.3 Instruction Register ................................................................................45

2.10.4 Boundary Scan Register ........................................................................45

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

Datasheet

Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782

Figures

LXT 9782 Block Diagram ...................................................................................... 9

LXT9782HC (PQFP) Preliminary Pin Assignments............................................10

LXT9782BC (PBGA) Preliminary Pin Assignments............................................11

LXT9762HC (PQFP) Preliminary Pin Assignments ............................................12

LXT97x2 Interfaces ............................................................................................21

Port Address Scheme .........................................................................................23

Management Interface Read Frame Structure ...................................................23

Management Interface Write Frame Structure ...................................................24

Interrupt Logic ....................................................................................................24

Initialization Sequence .......................................................................................26

Hardware Control Settings .................................................................................27

Link Establishment Process ...............................................................................29

Simplified SMII Application Diagram ..................................................................30

100Mbps Serial MII Data Flow ...........................................................................31

Serial MII Transmit Synchronization ..................................................................32

Loopback Paths...................................................................................................33

Serial MII Receive Synchronization ....................................................................33

100BASE-X Frame Format ...............................................................................34

Protocol Sublayers .............................................................................................36

Serial LED Streams.............................................................................................42

LED Pulse Stretching ..........................................................................................43

Quick Status Register..........................................................................................44

Power and Ground Supply Connections ............................................................49

Typical Twisted-Pair Interface ............................................................................50

Typical Fiber Interface ........................................................................................51

Typical Serial LED Interface................................................................................52

MII Sync Timing...................................................................................................56

100BASE-TX Receive Timing .............................................................................56

SMII Output Delay Test Setup............................................................................57

100BASE-TX Transmit Timing ............................................................................57

100BASE-FX Receive Timing .............................................................................58

100BASE-FX Transmit Timing ............................................................................58

10BASE-T Receive Timing..................................................................................59

10BASE-T Transmit Timing.................................................................................59

Auto-Negotiation and Fast Link Pulse Timing ....................................................60

Fast Link Pulse Timing .......................................................................................60

MDIO Write Timing (MDIO Sourced by MAC) ....................................................61

MDIO Read Timing (MDIO Sourced by PHY) ....................................................61

Power-Up Timing ................................................................................................62

Reset and Power-Down Recovery Timing .........................................................62

PHY Identifier Bit Mapping ..................................................................................68

LXT97x2 PQFP Package Specification...............................................................77

LXT97x2 PBGA Package Specification...............................................................78

Datasheet

LXT9782BC Related Products

	LXT9782BC	LXT9762HC	LXT9782HC
Description	Ethernet Transceiver, PBGA272, PLASTIC, BGA-272	Ethernet Transceiver, PQFP208, PLASTIC, QFP-208	Ethernet Transceiver, PQFP208, PLASTIC, QFP-208
Maker	Inphi Corporation	Inphi Corporation	Inphi Corporation
package instruction	BGA,	FQFP,	FQFP,
Reach Compliance Code	compliant	compliant	compliant
JESD-30 code	S-PBGA-B272	S-PQFP-G208	S-PQFP-G208
length	27 mm	28 mm	28 mm
Number of functions	1	1	1
Number of terminals	272	208	208
Maximum operating temperature	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	FQFP	FQFP
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.32 mm	4.1 mm	4.1 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.5 mm	0.5 mm
Terminal location	BOTTOM	QUAD	QUAD
width	27 mm	28 mm	28 mm
Base Number Matches	1	1	1

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