IS61LPS12832A-250TQI datasheet, PDF

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IS61LPS12832A-250TQI: Description128KX32 CACHE SRAM, 2.6ns, PQFP100, TQFP-100; Categorystorage storage; File Size163KB，26 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LPS12832A-250TQI Overview

128KX32 CACHE SRAM, 2.6ns, PQFP100, TQFP-100

IS61LPS12832A-250TQI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4194304 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.075 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

ISSI

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

LPS: V

3.3V + 5%, V

DDQ

3.3V/2.5V + 5%

VPS: V

2.5V + 5%, V

DDQ

2.5V + 5%

• JEDEC 100-Pin TQFP, 119-ball PBGA, and

165-ball PBGA packages

• Automotive temperature available

• Lead Free available

PRELIMINARY INFORMATION

FEBRUARY 2005

DESCRIPTION

The

ISSI

IS61(64)LPS12832A, IS61(64)LPS/VPS12836A

and IS61(64)LPS/VPS25618A are high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and network-

ing applications. The IS61(64)LPS12832A is organized as

131,072 words by 32 bits. The IS61(64)LPS/VPS12836A

is organized as 131,072 words by 36 bits. The IS61(64)LPS/

VPS25618A is organized as 262,144 words by 18 bits.

Fabricated with

ISSI

's advanced CMOS technology, the

device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single mono-

lithic circuit. All synchronous inputs pass through regis-

ters controlled by a positive-edge-triggered single clock

input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

Units

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

10/07/04

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