PT7M7803/7809-7812/7823-7825
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
μP
Supervisor Circuits
Features
Description
The PT7M78xx family microprocessor (P)
supervisory circuits are targeted to improve reliability
and accuracy of power-supply circuitry in
P
systems.
These devices reduce the complexity and number of
components required to monitor power-supply and
battery functions.
The main functions are:
1. Asserting reset output during power-up, power-
down and brownout conditions for
P
system.
2. Detecting power failure or low-battery
conditions with a 1.25V threshold detector.
3. Watchdog functions
4. Manual reset.
Precision supply-voltage monitor
- 4.63V (PT7M78xxL)
- 4.38V (PT7M78xxM)
- 3.08V (PT7M78xxT)
- 2.93V (PT7M78xxS)
- 2.63V (PT7M78xxR)
- 2.32V (PT7M78xxZ)
- 2.20V (PT7M78xxY)
- 4.00V (PT7M78xxJ)
- 2.25V (PT7M78xxK)
- 2.80V (PT7M78xxG)
200ms reset pulse width
Debounced CMOS-compatible manual-reset input
(7811, 7812, 7823, 7825)
Reset Output Signal for Watchdog and Power
Abnormal, Manual Reset
Reset Push-Pull output (PT7M7809,7811,7823,
7824,7825)
Reset Open-Drain output (PT7M7803)
Voltage monitor for power-fail or low battery
warning
Guaranteed RESET/RESET valid at V
CC
=1.0V
Applications
Power-supply circuitry in
P
systems
Function Comparison Table
Part No.
1
2
3
4
5
6
7
8
PT7M7803
PT7M7809
PT7M7810
PT7M7811
PT7M7812
PT7M7823
PT7M7824
PT7M7825
RESET output
Push-Pull
Open-Drain
-
-
-
-
-
-
-
-
-
-
RESET output
(push-pull)
-
-
-
-
Manual Reset
Input
-
-
-
-
Power Fail
Detector
(1.25V)
-
-
-
-
-
-
-
-
Watchdog
Input
-
-
-
-
-
-
2013-11-0015
1
PT0109-19
12/12/13
PT7M7803/7809-7812/7823-7825
μP
Supervisor Circuits
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Configuration
SOT23-3
PT7M7803
PT7M7809
1
GND
1
SOT143
PT7M7810
GND
1
PT7M7811
GND
VCC
4
1
PT7M7812
GND
VCC
4
VCC
3
VCC
3
2
RESET
2
RESET
2
RESET
MR
3
2
RESET
MR
3
SOT23-5
PT7M7811
1
GND
VCC
5
1
PT7M7812
GND
VCC
5
2
NC
2
NC
3
RESET
MR
4
3
RESET
MR
4
PT7M7823
1
RESET
VCC
5
1
PT7M7824
RESET
VCC
5
PT7M7825
1
RESET
VCC
5
2
GND
2
GND
2
GND
3
MR
WDI
4
3
RESET
WDI
4
3
RESET
MR
4
SOT23-6
PT7M7342
PT7M7343
1
VCC
RESET
6
1
PT7M7344
VCC
RESET
6
1
PT7M7345
VCC
RESET
6
2
GND
MR
5
2
GND
MR
5
2
GND
RESET
5
3
PFI
PFO
4
3
PFI
PFO
4
3
PFI
PFO
4
2013-11-0015
2
PT0109-19
12/12/13
PT7M7803/7809-7812/7823-7825
μP
Supervisor Circuits
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Description
Pin
MR
Type
I
Description
Manual-Reset: (CMOS).
Active low. Pull low to force a reset. Reset remains asserted for the duration of
the Reset Timeout Period after MR transitions from low to high. Leave unconnected or connected to VCC if
not used.
Supply Voltage.
Reset is asserted when V
CC
drops below the Reset Threshold Voltage (V
RST
). Reset
remains asserted until V
CC
rises above V
RST
and keep asserted for the duration of the Reset Timeout Period
(t
RS
) once V
CC
rises above V
RST
.
Ground Reference
for all signals.
Power-Fail Voltage Monitor Input.
When PFI <V
PFT
, PFO goes low. Connect PFI to GND or Vcc when
not used.
Power-Fail Output:
it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
Watchdog Input (CMOS).
If WDI remains high or low for the duration of the watchdog timeout period
(t
WD
), the internal watchdog timer trigger a reset output. Floating WDI or connecting WDI to a high-
impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever
reset is asserted or WDI occurs a rising or falling edge.
Active-Low Reset Output (Push-Pull or Open-Drain).
It goes low when Vcc is below the reset threshold.
It remains low for about 200ms after one of the following occurs: Vcc rises above the reset threshold
(VRST), the watchdog triggers a reset, or MR goes from low to high.
The inverse of RESET,
active high. Whenever RESET is high, RESET is low.
No connection.
VCC
Power
GND
PFI
PFO
-
I
O
WDI
I
RESET
O
O
-
RESET
NC
Block Diagram
PT7M7823/24/25 Block Diagram
Watchdog
Transition Detector
V cc
WDI
Watchdog Timer
Timebase for Reset
& Watchdog
RESET
(RESET)
MR
Reset Generator
Vcc
V
RST
PFI
1.25V
PFO
2013-11-0015
3
PT0109-19
12/12/13
PT7M7803/7809-7812/7823-7825
μP
Supervisor Circuits
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PT7M7811/12 Block Diagram
Maximum Ratings
Storage Temperature ............................................................-65
o
C to +150
o
C
Ambient Temperature with Power Applied.......................... -40
o
C to +85
o
C
Supply Voltage to Ground Potential (Vcc to GND) ..............-0.3V to +7.0V
DC Input Voltage (All inputs except Vcc and GND)......-0.3V to V
CC
+0.3V
DC Output Current (All outputs) ..........................................................20mA
Power Dissipation .......................................... 320mW (Depend on package)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended Operation Conditions
Sym
V
CC
V
IH
V
IL
T
A
Description
Supply Voltage for 78xxL/M/J
Supply Voltage for 78xxT/S
Supply Voltage for 78xxR/Z/Y/K/G
Input High Voltage
Input Low Voltage
Operating Temperature
Test Conditions
-
-
-
-
-
-
Min
4.5
3.0
2.7
0.7V
CC
-
-40
Typ
5.0
3.3
3.0
-
-
-
Max
5.5
5.5
5.5
-
0.3V
CC
85
Unit
V
V
V
V
V
℃
2013-11-0015
4
PT0109-19
12/12/13
PT7M7803/7809-7812/7823-7825
μP
Supervisor Circuits
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical Characteristics
(V
CC
= V
RN
+ 5% to 5.5V, T
A
= -40~85º unless otherwise noted.)(Note 1)
C,
Symbol
V
CC
I
CC
V
IH
V
IL
V
RST
Description
Operating Voltage Range
Supply Current
Input High Voltage
Input Low Voltage
Threshold Voltage(Falling-
edge)(Note
2)
Vcc = 5V, No
load
Pin: MR, WDI
Pin: MR, WDI
T
A
= 25º
C
T
A
= -40 ~ 85º
C
Vcc varies
between
V
RN
±5%
78xx
7823/24/25L/M
7823/24/25
T/S/R/K/Z/Y
Others
Test Conditions
-
7803/09/10/11/12
7823/24/25
Min
1.0
-
-
0.7V
CC
-
V
RN
- 1.5%
V
RN
- 2.5%
-
-
-
Vcc-1.5
0.8×
Vcc
0.8×
Vcc
0.8×
Vcc
Vcc-1.5
0.8×
Vcc
-
-
-
-
-
-20
-
-
10
Typ
-
10
13
-
-
V
RN
V
RN
12
4
50
-
-
-
-
-
-
-
-
-
-
120
-15
-
-
20
Max
5.5
30
36
-
0.3V
CC
V
RN
+ 1.5%
V
RN
+ 2.5%
-
-
-
-
-
-
-
-
-
0.4
0.3
0.3
1
160
-
800
µA
400
30
µA
µA
V
V
V
V
mV
V
Unit
V
µA
V
V
V
RTH
Reset Threshold Hysteresis
(Note
2)
Vcc
4.5V Isource=800µ
A
Output High
Voltage(Except
7823/24/25)
V
OH
Output High
Voltage(7823/24/25)
Vcc
2.7V Isource=500µ
A
Vcc
1.8V Isource=150µ
A
Vcc
1.0V Isource=4µ
A
7823/24/25L/M, Vcc=V
RST
Isource=120µ
A
7823/24/25T/S/R/K, Vcc=V
RST
Isource=30µA
Vcc
4.5V Isink=3.2mA
Vcc
2.7V Isink=1.2mA
Vcc
1.0V Isink=100µ
A
I
LKG
Open-Drain Output
Leakage Current
Average WDI Input
Current (Note
3)
RESET Output Short-
Circuit Current (only for
PT7M7823/24/25)
MR pull-up resistor
(internal)
V
CC
> V
TH(MAX)
for 7803
WDI connected to V
CC
: 5.5V
WDI connected to GND
PT7M782xL/M, RESET=0V,
Vcc=5.5V
PT7M782xT/S/R/K/Z/Y, RESET=0V,
Vcc=3.6V
PT7M7811/7812
V
OL
Output Low Voltage
I
WDI
I
source
k
PT7M7823/7824/7825
35
52
75
Note:
1. Parameters of room temperature guaranteed by production test and parameters of full-temperature guaranteed by design.
2. Valid for both RESET and RESET. V
RST
(
V
RTH
-
) is the Reset threshold voltage when V
CC
from high to low level, and
V
RTH
+ is the Reset threshold voltage when V
CC
from low to high level. V
RN
is nominal reset threshold voltage.
3. WDI is internally serviced within the watchdog period if WDI is left unconnected.
r
2013-11-0015
5
PT0109-19
12/12/13
京公网安备 11010802033920号
EEWORLD
