R5107G Series
Watchdog Timer Equipped with Manual Reset with VD
The R5107G Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single chip.
R5107G monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset signal when a
malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted with an external capacitor
with a high degree of accuracy. The R5107G is equipped with the function that inhibits clock monitoring of the WDT (INH) and manual reset
(MR) that also stops the VD.
FEATURES
•
Supply Current (I
SS
) ························Typ. 11μA (V
DD
=-V
DET
+0.5V,
•
Operating Voltage Range (V
DD
) ······0.9V to 6.0V
Clock pulse input)
(VD Section)
•
Detector Threshold Range (-V
DET
) ···1.5V to 5.5V (internally fixed)
•
Detector Threshold Accuracy ··········± 1%
•
Temp. coeff. of Detector Threshold ···Typ.
±
100ppm/°C
•
Output Delay Time (t
PLH
) ················· Typ. 370ms (C
D
=0.1μF)
•
Output Delay Time Accuracy ··········± 16% (-40°C
<
Topt
<
105°C)
=
=
(WDT Section)
•
Watchdog Timeout Period(t
WD
) ······· Typ. 310ms (C
TW
=0.1μF)
•
Reset Hold Time of WDT(t
WR
)········· Typ. 34ms (C
TW
=0.1μF)
•
Watchdog Timeout Period Accuracy ····
±
33% (-40°C
<
Topt
<
105°C)
=
=
•
Package·········································· SSOP-8G
(The above shows specification at Topt=25
°
C. Design assurance value at -40
°
C
<
Topt
<
105
°
C is also available. For details, please refer to the datasheet.)
=
=
BLOCK DIAGRAMS
R5107Gxx1A
(Nch. open drain output)
MR
V
DD
V
DD
TYPICAL APPLICATION
R5107Gxx1C
(CMOS output)
Power Supply
MR
Microprocessor
V
DD
R
8
V
DD
C
D
Vref2
Vref1
RESETB
1
RESET
I/O
C
D
Vref2
Vref1
6
INH R5107Gxx1A
GND
GND
C
TW
WATCHDOG
TIMER
CLOCK
DETECTOR
2
MR
SW SW
Series
GND
SCK
5
C
TW
SCK
WATCHDOG
TIMER
CLOCK
DETECTOR
SCK
3
C
D
C
D
C
TW
7
C
TW
4
RESETB
INH
RESETB
INH
SELECTION GUIDE
Package
SSOP-8G
Quantity per Reel
3,000 pcs
Part No.
R5107G
.xx.1.
∗
-TR-F
.xx.
: Specify the detector threshold within the range 1.5V (.15.) to 5.5V (.55.)
in 0.1V steps.
.
: Select the output type from (.A.) Nch. open drain or (.C.) CMOS.
.∗
PACKAGE (Top View)
SSOP-8G
8 7 6 5
TIMING CHART
V
DD
-V
DET
+V
DET
V
INH
1
2
3
4
V
MR
1
2
3
4
5
6
7
8
RESETB
MR
C
D
GND
SCK
INH
C
TW
V
DD
Output pin for Reset "L" signal
Manual reset pin
Ext. Cap. pin for setting output
delay time of VD
Ground pin
Watchdog timer clock input pin
Inhibit pin
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
Power supply pin
t
PHL
t
PHL
t
PLH
t
PLH
V
CD
+V
TCD
-V
TCD
t
WD
V
ref2H
t
WDI
t
WD
V
CTW
V
ref2L
t
WR
t
WR
V
SCK
t
PLH
t
MR
V
RESETB
APPLICATION
•
Monitoring of the power system of devices equipped with microprocessors
No.EK-170-091101
∗t
PHL
: Output delay time
∗t
WDI
: t
WD
/10 (SCK pulses input during this period are ignored.)
CMOS Microprocessor Supervisory
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