M29F002BT, M29F002BNT
M29F002BB, M29F002BNB
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
■
SINGLE 5V ± 10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 45 ns
PROGRAMMING TIME
– 8 µs by Byte typical
7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 4 Main Blocks
PLCC32 (K)
TSOP32 (N)
(8 x 20mm)
■
■
■
■
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION
MODE
LOW POWER CONSUMPTION
– Standby and Automatic Standby
Figure 1. Logic Diagram
■
VCC
■
18
A0-A17
W
E
G
RP
M29F002BT
M29F002BB
M29F002BNT
M29F002BNB
8
DQ0-DQ7
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M29F002BT: B0h
– Top Device Code M29F002BNT: B0h
– Bottom Device Code M29F002BB: 34h
– Bottom Device Code M29F002BNB: 34h
■
■
■
ECOPACK
®
PACKAGES AVAILABLE
VSS
AI02957B
September 2005
1/21
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Figure 2. PLCC Connections
Figure 3. TSOP Connections
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M29F002BT
M29F002BB
M29F002BNB
A11
A9
A8
A13
A14
A17
W
VCC
RP
A16
A15
A12
A7
A6
A5
A4
1
32
25
8
9
M29F002BT
M29F002BB
25
24
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
16
17
AI02958
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A12
A15
A16
RP
VCC
W
A17
AI02959B
SUMMARY DESCRIPTION
The M29F002B is a 2 Mbit (256Kb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM. The
M29F002B is fully backward compatible with the
M29F002.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 20mm),
PLCC32 packages and it is supplied with all the
bits erased (set to ’1’).
In order to meet environmental requirements, ST
offers the M29F002B in ECOPACK
®
packages.
ECOPACK packages are Lead-free. The category
of second Level Interconnect is marked on the
package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum rat-
ings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
2/21
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 1. Signal Names
A0-A17
DQ0-DQ7
E
G
W
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
M29F002BT, M29F002BB:
Reset/Block Temporary Unprotect
M29F002BNT, M29F002BNB:
Not Connected Internally
Supply Voltage
Ground
RP
V
CC
V
SS
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the select-
ed address during a Bus Read operation. During
Bus Write operations they represent the com-
mands sent to the Command Interface of the inter-
nal state machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Table 3. Top Boot Block Addresses,
M29F002BT, M29F002BNT
#
6
5
4
3
2
1
0
Size
(Kbytes)
16
8
8
32
64
64
64
Address Range
3C000h-3FFFFh
3A000h-3BFFFh
38000h-39FFFh
30000h-37FFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected. On the M29F002BNT the pin is not
connected internally and this feature is not avail-
able.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or t
PLYH
, whichever occurs last. See Table 15 and
Figure 11, Reset/Temporary Unprotect AC Char-
acteristics for more details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Reset/Block Temporary Unprotect can be left un-
connected. A weak internal pull-up resistor en-
sures that the memory always operates correctly.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
Table 4. Bottom Boot Block Addresses,
M29F002BB
#
6
5
4
3
2
1
0
Size
(Kbytes)
64
64
64
32
8
8
16
Address Range
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
3/21
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Table 2. Absolute Maximum Ratings
(1)
Symbol
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
T
A
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–40 to 85
–40 to 125
–50 to 125
–65 to 150
–0.6 to 6
–0.6 to 6
–0.6 to 13.5
Unit
°C
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 5, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the Data
Inputs/Outputs pins are placed in the high-imped-
ance state and the Supply Current is reduced to the
Standby level.
When Chip Enable is at V
IH
the Supply Current is re-
duced to the TTL Standby Supply Current, I
CC2
. To
further reduce the Supply Current to the CMOS
Standby Supply Current, I
CC3
, Chip Enable should
be held within V
CC
± 0.2V. For Standby current lev-
els see Table 11, DC Characteristics.
During program or erase operations the memory will
continue to use the Program/Erase Supply Current,
I
CC4
, for Program or Erase operations until the oper-
ation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic Stand-
by where the internal Supply Current is reduced to
the CMOS Standby Supply Current, I
CC3
. The Data
Inputs/Outputs will still output data if a Bus Read op-
eration is in progress.
Special Bus Operations
Additional bus operations can be performed to read
the Electronic Signature and also to apply and re-
move Block Protection. These bus operations are
intended for use by programming equipment and
are not usually used in applications. They require
V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device code,
that can be read to identify the memory. These
codes can be read by applying the signals listed in
Table 5, Bus Operations.
4/21
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB
Block Protection
and
Blocks Unprotection.
Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The commands are summarized in Table 6, Com-
mands. Refer to Table 6 in conjunction with the
text descriptions below.
Read/Reset Command.
The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10
µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command.
The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
IL
and A1 = V
IL
. The other address bits
may be set to either V
IL
or V
IH
. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = V
IH
and A1 = V
IL
. The other
address bits may be set to either V
IL
or V
IH
. The
Device Code for the M29F002BT is B0h, the
M29F002BNT is B0h and the M29F002BB is 34h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V
IL
,
A1 = V
IH
, and A13-A17 specifying the address of
the block. The other address bits may be set to ei-
ther V
IL
or V
IH
. If the addressed block is protected
then 01h is output on the Data Inputs/Outputs, oth-
erwise 00h is output.
Program Command.
The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 7. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
Table 5. Bus Operations
Operation
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Note: X = V
IL
or V
IH
.
E
V
IL
V
IL
X
V
IH
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
Address Inputs
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Data
Inputs/Outputs
Data Output
Data Input
Hi-Z
Hi-Z
20h
B0h (M29F002BT)
B0h (M29F002BNT)
34h (M29F002BB)
V
IL
V
IL
V
IH
5/21
PCB Design
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