Latch-Up Current ..................................................... >200 mA
Operating Range
Device
WCMC4016V7B
Range
Industrial
Ambient Temperature
–25°C to +85°C
V
CC
2.70V to 3.30V
Electrical Characteristics
Over the Operating Range
WCMC4016V7B-55
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current — CMOS
Inputs
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
I
OH
= –0.1 mA
I
OL
= 0.1mA
V
CC
= 2.7V to 3.3V
V
CC
= 2.70V
V
CC
= 2.70V
0.8 *
V
CC
–0.4
–1
–1
14
1
150
Test Conditions
Min. Typ.
[3]
Max.
2.7
V
CC
–
0.4
0.4
V
CC
0.8 *
+ 0.4V V
CC
0.4
+1
+1
22
5
250
–0.4
–1
–1
8
1
150
3.0
3.3
WCMC4016V7B-70
Min. Typ.
[3]
Max. Unit
2.7
V
CC
–
0.4
0.4
V
CC
+ 0.4V
0.4
+1
+1
15
5
250
3.3
V
V
V
V
V
µA
µA
mA
mA
µA
I
SB1
V
CC
= 3.3V
CE > V
CC
−
0.2V
V
IN
>V
CC
– 0.2V, V
IN
< 0.2V)
f = f
MAX
(Address and Data
Only), f = 0 (OE, WE, BHE
and BLE), V
CC
= 3.30V
I
SB2
Automatic CE
CE > V
CC
– 0.2V
V
CC
= 3.3V
Power-Down
V
IN
> V
CC
– 0.2V or
Current — CMOS V
IN
< 0.2V, f = 0, V
CC
= 3.30V
Inputs
17
40
17
40
µA
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Notes:
5. V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
6. V
IH(Max)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7. Overshoot and undershoot specifications are characterized and are not 100% tested.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-14034 Rev. *D
Page 3 of 10
WCMC4016V7B
Thermal Resistance
[8]
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA
/ JESD51.
Symbol
Θ
JA
Θ
JC
BGA
55
17
Unit
°C/W
°C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
GND
30 pF
INCLUDING
JIG AND
SCOPE
R2
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalentto:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Switching Characteristics
Over the Operating Range
[9]
55 ns
[13]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK [13]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[10, 12]
OE HIGH to High Z
[10, 12]
CE LOW to Low Z
CE HIGH to High
[10, 12]
70 ns
Min.
70
55
70
10
55
25
70
35
5
25
25
5
25
55
25
70
5
10
0
25
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
55
[13]
5
Max.
5
2
Z
[10, 12]
5
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[10, 12]
BLE/BHE HIGH to HIGH Z
[10, 12]
Address Skew
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0V to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
10. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
11. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
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