RD28F3208C3T110 datasheet, PDF

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RD28F3208C3T110: DescriptionMemory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA68, 8 X 14 MM, 1.40 MM HEIGHT, STACK, CSP-68; Categorystorage storage; File Size601KB，66 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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RD28F3208C3T110 Overview

Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA68, 8 X 14 MM, 1.40 MM HEIGHT, STACK, CSP-68

RD28F3208C3T110 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	BGA
package instruction	LFBGA, BGA68,8X12,32
Contacts	68
Reach Compliance Code	compliant
Maximum access time	110 ns
Other features	SRAM IS ORGANISED AS 512K X 16
JESD-30 code	R-PBGA-B68
JESD-609 code	e0
length	14 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Number of functions	1
Number of terminals	68
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA68,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.000006 A
Maximum slew rate	0.055 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm
Base Number Matches	1

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3 Volt Advanced+ Stacked Chip Scale

Package Memory

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Preliminary Datasheet

Product Features

Flash Memory Plus SRAM

— Reduces Memory Board Space

Required, Simplifying PCB Design

Complexity

Stacked Chip Scale Package Technology

— Smallest Memory Subsystem Footprint

— 16-Mbit Flash + 2-Mbit SRAM:

Area: 8 mm by 10 mm, Height: 1.4 mm

— 32-Mbit Flash + 8-Mbit SRAM:

Area: 8 mm by 14mm, Height: 1.4 mm

— 32-Mbit Flash + 4-Mbit SRAM,

16-Mbit Flash + 4-Mbit SRAM:

Area: 8 mm by 12 mm, Height: 1.4 mm

Advanced SRAM Technology

— 70 ns Access Time

— Low Power Operation

— Low Voltage Data Retention Mode

Flash Data Integrator (FDI) Software

— Real-Time Data Storage and Code

Execution in the Same Memory Device

— Full Flash File Manager Capability

Advanced+ Boot Block Flash Memory

— 90 ns 16-Mb Access Time at 2.7 V

— 100 ns 32-Mb Access Time at 2.7 V

— 110 ns 32-Mb Access Time at 2.7 V with

8-Mbit SRAM

— Instant, Individual Block Locking

— 128-bit Protection Register

— 12 V Production Programming

— Ultra Fast Program and Erase Suspend

— Extended Temperature –25 °C to +85 °C

Blocking Architecture

— Block Sizes for Code + Data Storage

— 4-Kword Parameter Blocks (for data)

— 64-Kbyte Main Blocks (for code)

— 100,000 Erase Cycles per Block

Low Power Operation

— Async Read Current: 9 mA

— Standby Current: 10

µA

— Automatic Power Saving Mode

0.25

µm

ETOX™ VI Flash Technology

Industry Compatibility

— Sourcing Flexibility and Stability

The 3 Volt Advanced+ Stacked Chip Scale Package (Stacked-CSP) memory delivers a feature-

rich solution for low-power applications. Stacked-CSP memory devices incorporate flash

memory and static RAM in one package with low voltage capability to achieve the smallest

system memory solution form-factor together with high-speed, low-power operations. The flash

memory offers a protection register and flexible block locking to enable next generation security

capability. Combined with the Intel-developed Flash Data Integrator (FDI) software, the

Stacked-CSP memory provides you with a cost-effective, flexible, code plus data storage

solution.

Notice:

This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Order Number: 290666-007

February, 2001

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Contents

1.0

Introduction

.................................................................................................................. 1

1.1

1.2

1.3

1.4

Document Conventions ......................................................................................... 1

Product Overview .................................................................................................. 1

Package Ballout .................................................................................................... 2

Signal Definitions................................................................................................... 3

Bus Operation ....................................................................................................... 5

2.1.1 Read......................................................................................................... 5

2.1.2 Output Disable.......................................................................................... 6

2.1.3 Standby .................................................................................................... 6

2.1.4 Flash Reset .............................................................................................. 7

2.1.5 Write ......................................................................................................... 7

Read Array (FFh) .................................................................................................. 7

Read Identifier (90h).............................................................................................. 7

Read Status Register (70h)................................................................................... 8

3.3.1 Clear Status Register (50h) ...................................................................... 8

Read Query (98h).................................................................................................. 9

Word Program (40h/10h)....................................................................................... 9

3.5.1 Suspending and Resuming Program (B0h/D0h) ...................................... 9

Block Erase (20h)................................................................................................10

3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................10

Instant, Individual Block Locking .........................................................................12

3.7.1 Block Locking Operation Summary ........................................................12

3.7.2 Locked State ..........................................................................................13

3.7.3 Unlocked State .......................................................................................13

3.7.4 Lock-Down State ....................................................................................13

3.7.5 Reading a Block’s Lock Status ...............................................................13

3.7.6 Locking Operation during Erase Suspend..............................................14

3.7.7 Status Register Error Checking..............................................................14

128-Bit Protection Register .................................................................................15

3.8.1 Reading the Protection Register ............................................................15

3.8.2 Programming the Protection Register (C0h) ..........................................15

3.8.3 Locking the Protection Register .............................................................16

Additional Flash Features....................................................................................16

3.9.1 Improved 12 Volt Production Programming ...........................................16

3.9.2 F-VPP £ VPPLK for Complete Protection ..............................................17

Absolute Maximum Ratings.................................................................................17

Operating Conditions...........................................................................................18

Capacitance ........................................................................................................18

DC Characteristics ..............................................................................................19

Flash AC Characteristics—Read Operations ......................................................23

Flash AC Characteristics—Write Operations ......................................................25

2.0

Principles of Operation

............................................................................................ 5

2.1

3.0

Flash Memory Modes of Operation

..................................................................... 7

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

Electrical Specifications

........................................................................................17

4.1

4.2

4.3

4.4

4.5

4.6

PRELIMINARY

iii

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.7

4.8

4.9

4.10

4.11

Flash Erase and Program Timings(1) ................................................................. 26

Flash Reset Operations ...................................................................................... 28

SRAM AC Characteristics—Read Operations(1)................................................ 29

SRAM AC Characteristics—Write Operations(1, 2) ............................................ 31

SRAM Data Retention Characteristics(1) —Extended Temperature .................. 32

5.0

6.0

Migration Guide Information

............................................................................... 33

System Design Considerations

.......................................................................... 34

6.1

Background ......................................................................................................... 34

6.1.1 Flash + SRAM Footprint Integration....................................................... 34

6.1.2 Advanced+ Boot Block Flash Memory Features .................................... 34

Flash Control Considerations.............................................................................. 34

6.2.1 F-RP# Connected to System Reset ....................................................... 35

6.2.2 F-VCC, F-VPP and F-RP# Transition..................................................... 35

Noise Reduction.................................................................................................. 36

Simultaneous Operation...................................................................................... 37

6.4.1 SRAM Operation during Flash “Busy” .................................................... 38

6.4.2 Simultaneous Bus Operations................................................................ 38

Printed Circuit Board Notes................................................................................. 38

System Design Notes Summary ......................................................................... 38

6.2

6.3

6.4

6.5

6.6

7.0

8.0

Ordering Information

.............................................................................................. 39

Additional Information

........................................................................................... 39

Program/Erase Flowcharts

............................................................................. 40

CFI Query Structure

........................................................................................... 46

Word-Wide Memory Map Diagrams

............................................................. 53

Device ID Table

.................................................................................................... 55

Protection Register Addressing

................................................................... 56

Mechanical and Shipping Media Details

................................................... 57

Appendix A

Appendix B

Appendix C

Appendix D

Appendix E

Appendix F

PRELIMINARY

RD28F3208C3T110 Related Products

	RD28F3208C3T110	RD28F3204C3B100	RD28F3204C3B110	RD28F3208C3T100	RD28F3202C3B110	RD28F3208C3B110	RD28F3202C3T110
Description	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA68, 8 X 14 MM, 1.40 MM HEIGHT, STACK, CSP-68	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA72, 8 X 12 MM, 1.40 MM HEIGHT, STACK, CSP-72	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA68, 8 X 14 MM, 1.40 MM HEIGHT, STACK, CSP-68	Memory IC	Memory Circuit, 2MX16, CMOS, PBGA72, 8 X 12 MM, 1.40 MM HEIGHT, STACK, CSP-72	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA68, 8 X 14 MM, 1.40 MM HEIGHT, STACK, CSP-68	Memory Circuit, 2MX16, CMOS, PBGA72, 8 X 12 MM, 1.40 MM HEIGHT, STACK, CSP-72
package instruction	LFBGA, BGA68,8X12,32	LFBGA, BGA68,8X12,32	LFBGA, BGA68,8X12,32	,	LFBGA,	LFBGA, BGA68,8X12,32	LFBGA,
Reach Compliance Code	compliant	unknow	unknow	unknown	unknown	compliant	unknown
Maker	Intel	-	-	Intel	Intel	Intel	Intel
Parts packaging code	BGA	BGA	BGA	-	BGA	BGA	BGA
Contacts	68	72	68	-	72	68	72
Maximum access time	110 ns	100 ns	110 ns	-	-	110 ns	-
Other features	SRAM IS ORGANISED AS 512K X 16	SRAM IS CONFIGURED AS 256 K X 16	SRAM IS ORGANISED AS 256K X 16	-	SRAM IS CONFIGURED AS 128 K X 16	SRAM IS ORGANISED AS 512K X 16	SRAM IS CONFIGURED AS 128 K X 16
JESD-30 code	R-PBGA-B68	R-PBGA-B72	R-PBGA-B68	-	R-PBGA-B72	R-PBGA-B68	R-PBGA-B72
length	14 mm	12 mm	14 mm	-	12 mm	14 mm	12 mm
memory density	33554432 bit	33554432 bi	33554432 bi	-	33554432 bit	33554432 bit	33554432 bit
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	-	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16	16	-	16	16	16
Mixed memory types	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	-	-	FLASH+SRAM	-
Number of functions	1	1	1	-	1	1	1
Number of terminals	68	72	68	-	72	68	72
word count	2097152 words	2097152 words	2097152 words	-	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	-	2000000	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	-	85 °C	85 °C	85 °C
Minimum operating temperature	-25 °C	-40 °C	-25 °C	-	-40 °C	-25 °C	-40 °C
organize	2MX16	2MX16	2MX16	-	2MX16	2MX16	2MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA	-	LFBGA	LFBGA	LFBGA
Encapsulate equivalent code	BGA68,8X12,32	BGA68,8X12,32	BGA68,8X12,32	-	-	BGA68,8X12,32	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	-	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	3 V	3 V	3 V	-	-	3 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	-	1.4 mm	1.4 mm	1.4 mm
Maximum standby current	0.000006 A	0.000045 A	0.000045 A	-	-	0.000006 A	-
Maximum slew rate	0.055 mA	0.055 mA	0.055 mA	-	-	0.055 mA	-
Maximum supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	-	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	-	3 V	3 V	3 V
surface mount	YES	YES	YES	-	YES	YES	YES
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS
Temperature level	OTHER	INDUSTRIAL	OTHER	-	INDUSTRIAL	OTHER	INDUSTRIAL
Terminal form	BALL	BALL	BALL	-	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	-	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm	-	8 mm	8 mm	8 mm
Base Number Matches	1	1	1	1	-	-	-

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