UT54ACS191/UT54ACTS191
Radiation-Hardened
Synchronous 4-Bit Up-Down Binary Counters
FEATURES
Single down/up count control line
counters
Fully synchronous in count modes
Asynchronously presetable with load control
radiation-hardened CMOS
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS191 and the UT54ACTS191 are synchronous 4-
bit reversible up-down binary counters. Synchronous counting
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each other
when so instructed. Synchronous operation eliminates the out-
put counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The di-
rection of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be
preset to either logic level by placing a low on the load input
and entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (15) counting up.
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PINOUTS
16-Pin DIP
Top View
B
B
A
1
15
3
13
V
A
RCO
LOAD
10
9
C
D/
Q
Q
SS
5
6
16-Lead Flatpack
Top View
16
Q
Q
CTEN
U
C
D
SS
DD
2
14
4
12
11
7
9
C
MAX/MIN
CLK
The ripple clock output (RCO) produces a low-level output
pulse under those same conditions but only while the clock input
is low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for high-
speed operation.
The devices are characterized over full military temperature
range of -55 C to +125
Rad-Hard MSI Logic
UT54ACS191/UT54ACTS191
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
10
1
UNITS
V
V
C
C
C
C/W
mA
W
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
125
Rad-Hard MSI Logic
UT54ACS191/UT54ACTS191
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
127
Rad-Hard MSI Logic
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