Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1046, DEI1047, DEI1148
OCTAL ARINC 429 LINE
RECEIVER
FEATURES
Octal ARINC 429 to TTL/CMOS logic line receivers
Operates from single +5V ± 10% or 3.3V ± 10% power supply
ARINC inputs internally protected to lightning requirements of DO-160 Level A3
Operates in high noise environment
o
Input Common Voltage Range: ± 20V
o
2V minimum Input hysteresis
Optional logic level TEST inputs on DEI1046.
Package Options
o
38L TSSOP, 4.4mm body (DEI1046/1047)
o
44L MQFP, 13.9mm footprint (DEI1148)
DEI1046/1047 PINOUT
IN1A
IN1B
IN2A
IN2B
IN3A
IN3B
IN4A
IN4B
IN5A
IN5B
IN6A
IN6B
IN7A
IN7B
IN8A
IN8A
* TESTA
* TESTB
19
20
1
38
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
Table 1a
PIN
15,13,11, 9,
7,5,3,1
16,14,12, 10,
8,6,4,2
18
19
21,23,25,27,
32,34,36,38
20,22,24,26,
31,33,35,37
29
28, 30
DEI1046/1047 Pin Description
DESCRIPTION
429 INPUTS. ARINC 429 format serial digital
data “A” inputs.
429 INPUTS. ARINC 429 format serial digital
data “B” inputs.
LOGIC INPUT. Test input A on DEI1046.
No Connect on DEI1047.
LOGIC INPUT. Test input B on DEI1046.
No Connect on DEI1047.
LOGIC OUTPUTS. CMOS/TTL format serial
digital data “A” outputs.
LOGIC OUTPUTS. CMOS/TTL format serial
digital data “B” outputs.
POWER INPUT. 5 VDC OR 3.3VDC.
POWER INPUT. Ground.
NAME
IN[8:1]A
IN[8:1]B
TESTA
TESTB
OUT[8:1]A
OUT[8:1]B
VDD
VSS
DEI1046/7
OUT3B
OUT4A
OUT4B
VSS
VDD
VSS
OUT5A
OUT5B
OUT6A
OUT6B
OUT7A
OUT7B
OUT8A
OUT8B
* No Connect on DEI1047
©2014 Device Engineering Inc.
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DEI1148 PINOUT
Table 1b DEI1148 Pin Description
PIN
15, 13, 11, 9, 2, 44, 42, 40
16, 14, 12, 10, 3, 1, 43, 41
5
6
7
8
19, 21, 23, 25, 32, 34, 36, 38
18, 20, 22, 24, 31, 33, 35, 37
29
27
NAME
IN[8:1]A
IN[8:1]B
TESTAA
TESTAB
TESTBA
TESTBB
OUT[8:1]A
OUT[8:1]B
VDD
VSS
DESCRIPTION
429 INPUTS. ARINC 429 format serial digital data “A” inputs.
429 INPUTS. ARINC 429 format serial digital data “B” inputs.
LOGIC INPUT. Test input A (+) for odd channels.
LOGIC INPUT. Test input A (-) for odd channels.
LOGIC INPUT. Test input B (+) for even channels.
LOGIC INPUT. Test input B (-) for even channels.
LOGIC OUTPUTS. CMOS/TTL format serial digital data “A” outputs.
LOGIC OUTPUTS. CMOS/TTL format serial digital data “B” outputs.
POWER INPUT. 5 VDC OR 3.3VDC.
POWER INPUT. Ground.
FUNCTIONAL DESCRIPTION
The DEI1046/7/1148 is a BiCMOS device which contains eight differential line receivers. Each receiver channel translates
incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs.
Each channel operates independently and meets the requirements of the ARINC 429 Digital Information Transfer Standard.
Refer to Figure 1 “DEI1046/7/1148 Block Diagram and Truth Table”.
The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20V common mode voltage
range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high frequency transients.
All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced
transient requirements of DO-160 Level A3.
©2014 Device Engineering Inc.
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The DEI1046 & 1148 devices provide logic level TEST inputs for built in system test. They force the outputs of all eight
receivers to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. The
DEI1046 has a single test port which controls all 8 channels. The DEI1148 has two test ports, each controlling 4 channels.
Test inputs are not bonded out on the DEI1047; they are internally connected to logic 0.
The ARINC inputs may optionally be connected to the ARINC bus through external 10K ohm series resistors. These resistors
may be added in combination with transient voltage suppressors to achieve lighting protection beyond the level 3 limits.
Block Diagram
Typical Channel
Truth Table
INPUTS
TEST INPUTS
(TTL/CMOS)
ARINC
INPUTS
OUTPUTS
TTL/CMOS
OUT A OUT B Logic
1
0
0
0
1
0
0
1
0
1
0
0
ONE
ZERO
NULL
ZERO
ONE
NULL
INA
OUTA
RESISTOR
NETWORK
AND
LIGHTNING
PROTECTION
TEST A TEST B A
IN
– B
IN
V
OUTPUT
AND
TEST
LOGIC
Comparators
INB
0
OUTB
0
0
0
1
0
1
Logic +1
Logic -1
NULL
X
X
X
0
0
0
1
TESTA
IINPUT
BUFFERS
TESTB
TO OTHER
TO OTHER
7
CHANNELS
7 CHANNELS
1
DEI1046 / 1047*
DEI1148
*Note: TEST inputs are not implemented on DEI1047. They are internally connected to logic 0.
Figure 1 DEI1046/1047/1148 Block Diagrams and Truth Table
©2014 Device Engineering Inc.
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ELECTRICAL DESCRIPTION
Table 2 Absolute Maximum Rating
PARAMETER
Supply Voltage (with respect to V
SS
)
Storage Temperature
Input Voltage, continuous (ARINC Inputs)
Input Voltage (Test Inputs)
Power Dissipation @ 85 °C
Junction Temperature, Tjmax, (limited by molding compound Tg)
Peak Body Temperature
Lightning Protection (ARINC 429 Channel Inputs and TESTA/TESTB Inputs)
Waveform 3 (2)
Waveform 4, 5A, 5B* (2) (3)
MIN
-0.3
-65
-40
V
SS
– 0.3
MAX
7.0
+150
+40
V
DD
+0.3
800
145
260
UNITS
V
°C
V
V
mW
°C
°C
V
V
-600
-300
+600
+300
ESD per
JEDEC A114-A Human Body Model
Notes:
-1000
1000
V
1.
2.
3.
Stresses above these limits can cause permanent damage.
Per DO160, Sect 22 Level 3A. See Figures 4-6.
Inputs can be protected to withstand higher stress by adding series resistors and shunt TVS on inputs. Inputs
withstand 1500V Waveform 5A when clipped 600V.
Table 3 Recommended Operating Conditions
PARAMETER
Supply Voltage
Logic Input Levels
Operating Temperature
-xEx
-xMx
SYMBOL
Vdd
V
TESTA,B
Ta
CONDITIONS
+5V ± 10%
+3.3V ± 10%
0 to Vdd
-55 to +85°C
-55 to +125°C
Table 4 Electrical Characteristics
Conditions:
Temperature: -55°C to +85°C (-xEx); -55°C to +125°C (-xMx)
V
DD
= +5V ± 10% or 3.3V ± 10%
PARAMETER
V
A
– V
B
= Logic +1
V
A
– V
B
= Logic -1
V
A
– V
B
= Logic Null
Input Hysteresis
V
A
– V
B
= Null to +1 transition
V
A
– V
B
= +1 to Null transition
V
A
– V
B
= Null to -1 transition
OUTA = 0 1
OUTA = 1 0
OUTB = 0 1
TEST CONDITION
OUTA = 1
OUTB = 1
OUTA = 0
OUTB = 0
SYMBOL
V
+1
V
-1
V
NULL
V
HY
V
T+1+
V
T+1-
V
T-1+
MIN
6.5
-6.5
-2.5
2.0
5.5
2.5
-6.5
NOM
10
-10
0
MAX
13
-13
2.5
UNITS
V
V
V
V
V
V
V
ARINC INPUTS
4.0
6.5
3.5
-5.5
©2014 Device Engineering Inc.
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Conditions:
Temperature: -55°C to +85°C (-xEx); -55°C to +125°C (-xMx)
V
DD
= +5V ± 10% or 3.3V ± 10%
PARAMETER
V
A
– V
B
= -1 to Null transition
TEST CONDITION
OUTB = 1 0
SYMBOL
V
T-1-
MIN
-3.5
-20
280K
140K
780K
390K
10
10
0.8
2.0
25
25
pF
pF
V
V
µA
µA
NOM
MAX
-2.5
UNITS
V
V
Input Common Mode Voltage
Logic +1, Null, Logic -1
V
CM
Range
Input Resistance
V
DD
open,
R
IN
IN
A
to IN
B
Shorted to V
SS
or +5V (1)
Input Resistance
V
DD
open,
R
S
IN
A
or IN
B
to V
SS
Shorted to V
SS
or +5V
Input Capacitance
V
DD
open,
C
IN
IN
A
to IN
B
Shorted to V
SS
or +5V (1)
Input Capacitance
V
DD
open,
C
S
IN
A
or IN
B
to V
SS
Shorted to V
SS
or +5V (1)
TEST INPUTS
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Current
Logic 1 Current
V
IL
= 0.8
V
IL
V
IH
I
IL
V
IH
= 2.0
I
IH
LOGIC OUTPUTS
I
OH
= -5mA (Vdd=5.0V)
I
OH
= -1.5mA (Vdd=3.3V)
V
OH
TTL Compatible
I
OL
= 5mA (Vdd=5.0V)
OUT A or OUT B
OUT A or OUT B
OUT A or OUT B
V
OL
+20
OUT A or OUT B
2.4
0.5
0.4
V
DD
–
50mV
V
SS
+
50mV
V
V
V
V
V
V
DD
Current
Notes:
1.
2.
I
OL
= -1.5mA (Vdd=3.3V)
V
OL
TTL Compatible
I
OH
= 100µA
V
OH
CMOS Compatible
V
OL
I
OL
= 100µA
CMOS Compatible
SUPPLY CURRENT
Data Rate = 0MHz,
A/BIN =open,
I
DD
A/BOUT=open,
Vdd = 5.5V or 3.63V
20
mA
Guaranteed by design, not production tested.
Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect
to Ground unless otherwise noted.
Table 5 Switching Characteristics
PARAMETER
INA/B to OUT A/B Prop Delay
INA/B to OUT A/B Prop Delay
OUT A/B rise time
OUT A/B fall time
TESTA/B to OUTA/B Prop
delay
TESTA/B to OUTA/B Prop
delay
TEST CONDITION
TESTA = TESTB = 0
C
L
= 50pF
TESTA = TESTB = 0
C
L
= 50pF
10% to 90%, C
L
= 50pF
10% to 90%, C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
SYMBOL
t
LH
t
HL
t
r
t
f
t
TOH
t
TOL
MAX
MAX
Vdd 3.3V Vdd 5V
1000
1000
50
50
100
100
900
900
25
25
60
60
UNITS
ns
ns
ns
ns
ns
ns
©2014 Device Engineering Inc.
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