KAD5612P-21Q72 datasheet, PDF - EEWORLD Datasheet

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KAD5612P-21Q72: Description2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72; Categorysemiconductor logic; File Size1MB，29 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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KAD5612P-21Q72 Overview

2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72

KAD5612P-21Q72 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	72
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	1.8 V
Maximum conversion time	0.0040 uS
Maximum linear error	0.0488 %
Processing package description	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes
Terminal form	NO
Terminal spacing	0.5000 mm
terminal coating	MATTE Tin
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Sampling Rate	250 MHz
Output format	Parallel, WORD
Type of converter	proprietary method
Number of digits	12
Output bit encoding	OFFSET binary, 2S supplementary binary, GRAY encoding
Number of analog channels	2
Sample and hold and track and hold	SAMPLE

KAD5612P-21Q72 Related Products

	KAD5612P-21Q72	KAD5612P-17Q72	KAD5612P-25Q72	KAD5612P	KAD5612P_09
Description	2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72	2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72	2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72	2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72	2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC72
Number of functions	1	1	1	1	1
Number of terminals	72	72	72	72	72
Maximum operating temperature	85 Cel	85 Cel	85 Cel	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel
Rated supply voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Maximum conversion time	0.0040 uS	0.0040 uS	0.0040 uS	0.0040 uS	0.0040 uS
Maximum linear error	0.0488 %	0.0488 %	0.0488 %	0.0488 %	0.0488 %
Processing package description	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72	10 × 10 MM, ROHS COMPLIANT, plastic, QFN-72
Lead-free	Yes	Yes	Yes	Yes	Yes
EU RoHS regulations	Yes	Yes	Yes	Yes	Yes
state	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS	CMOS	CMOS	CMOS
packaging shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes	Yes	Yes	Yes	Yes
Terminal form	NO	NO	NO	NO	NO
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	MATTE Tin	MATTE Tin	MATTE Tin	MATTE Tin	MATTE Tin
Terminal location	Four	Four	Four	Four	Four
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Sampling Rate	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz
Output format	Parallel, WORD	Parallel, WORD	Parallel, WORD	Parallel, WORD	Parallel, WORD
Type of converter	proprietary method	proprietary method	proprietary method	proprietary method	proprietary method
Number of digits	12	12	12	12	12
Output bit encoding	OFFSET binary, 2S supplementary binary, GRAY encoding	OFFSET binary, 2S supplementary binary, GRAY encoding	OFFSET binary, 2S supplementary binary, GRAY encoding	OFFSET binary, 2S supplementary binary, GRAY encoding	OFFSET binary, 2S supplementary binary, GRAY encoding
Number of analog channels	2	2	2	2	2
Sample and hold and track and hold	SAMPLE	SAMPLE	SAMPLE	SAMPLE	SAMPLE

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