Preliminary. Subject to Change Without Notice.
PRELIMINARY DATASHEET
DS3106
Line Card Timing IC
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3106 is a low-cost timing IC for telecom line
cards. The device accepts two reference clocks from
dual redundant system timing cards, continually
monitors both inputs, and performs manual reference
switching if the primary reference fails. The highly
programmable DS3106 supports numerous input and
output frequencies including frequencies required for
SONET/SDH, Synchronous Ethernet (1G, 10G and
100Mb/s), wireless basestations and CMTS systems.
PLL bandwidths from 18 Hz to 400 Hz are supported,
and a wide variety of PLL characteristics and device
features can be configured to meet the needs of
many different applications.
The DS3106 register set is backward compatible with
Semtech’s ACS8526 line card timing IC. The DS3106
pinout is similar but not identical to the ACS8526.
FEATURES
Advanced DPLL Technology
Programmable PLL bandwidth:18 Hz to 400 Hz
Manual Reference Switching
Holdover on Loss of Input Reference
Frequency Conversion Among SONET/SDH, PDH,
Ethernet, Wireless and CMTS Rates
2 Input Clocks
CMOS/TTL Signal Format (≤125 MHz)
Numerous Input Clock Frequencies Supported
- SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz
- Ethernet xMII: 2.5, 25, 125 MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Frame Sync: 2 kHz, 4 kHz, 8 kHz
- Custom:
Any Multiple of 2 kHz up to 125 MHz
2 Output Clocks
One CMOS/TTL Output (≤125 MHz)
One LVDS/LVPECL Output (≤312.50 MHz)
Two Optional Frame Sync Outputs: 2 kHz, 8 kHz
Numerous Output Clock Frequencies Supported
- SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz
- Ethernet xMII: 2.5, 25, 125, 156.25, 312.5 MHz
- PDH: N x DS1, N x E1, N x DS2, DS3, E3
- Other: 10, 10.24, 13, 30.72 MHz, plus other
frequencies available upon request
- Frame Sync: 2 kHz, 8 kHz
- Custom Clock Rates: Any Multiple of 2 kHz up to
77.76 MHz, Any Multiple of 8 kHz up to 311.04MHz
APPLICATIONS
SONET/SDH, Synchronous Ethernet, PDH and Other
Line Cards in WAN Equipment Including MSPPs,
Ethernet Switches, Routers, DSLAMs, and Wireless
Base Stations.
FUNCTIONAL DIAGRAM
IC3
IC4
DS3106
OC3
General
Suitable line card IC for stratum 3E/3/4, SMC, SEC
Internal Compensation for Master Clock Oscillator
SPI Processor Interface
1.8V Operation with 3.3V I/O (5V tolerant)
Industrial Operating Temperature Range
OC6 LVDS/LVPECL
ORDERING INFORMATION
FSYNC
MFSYNC
PART
DS3106GN
DS3106GN+
local
oscillator
TEMP
RANGE
-40 to 85°C
-40 to 85°C
PACKAGE
LQFP64
LQFP64, RoHS compliant
control status
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Preliminary. Subject to Change Without Notice.
DS3106
TABLE OF CONTENTS
1
2
3
4
5
6
7
STANDARDS COMPLIANCE ............................................................................................................................... 5
APPLICATION EXAMPLE..................................................................................................................................... 6
BLOCK DIAGRAM ................................................................................................................................................ 6
DETAILED DESCRIPTION ................................................................................................................................... 7
DETAILED FEATURES......................................................................................................................................... 8
PIN DESCRIPTIONS ............................................................................................................................................ 9
FUNCTIONAL DESCRIPTION............................................................................................................................ 12
7.1
7.2
7.3
7.4
Overview.................................................................................................................................................... 12
Device Identification and Protection .......................................................................................................... 12
Local Oscillator and Master Clock Configuration ...................................................................................... 12
Input Clock Configuration .......................................................................................................................... 12
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.5.3
7.6
7.7
Signal Format Configuration......................................................................................................... 13
Frequency Configuration .............................................................................................................. 13
Frequency Monitoring................................................................................................................... 14
Activity Monitoring ........................................................................................................................ 14
Selected Reference Activity Monitoring........................................................................................ 15
Input Clock Monitoring............................................................................................................................... 14
Input Clock Selection and Switching ......................................................................................................... 15
DPLL Architecture and Configuration........................................................................................................ 16
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
T0 DPLL State Machine ............................................................................................................... 17
Bandwidth..................................................................................................................................... 19
Damping Factor ............................................................................................................................ 20
Phase Detectors ........................................................................................................................... 20
Loss of Phase Lock Detection...................................................................................................... 21
Frequency and Phase Measurement ........................................................................................... 21
Input Jitter Tolerance.................................................................................................................... 21
Jitter Transfer ............................................................................................................................... 21
Output Jitter and Wander ............................................................................................................. 22
Signal Format Configuration......................................................................................................... 22
Frequency Configuration .............................................................................................................. 22
7.8
Output Clock Configuration ....................................................................................................................... 22
7.8.1
7.8.2
7.9
Microprocessor Interface ........................................................................................................................... 30
7.10 Reset Logic................................................................................................................................................ 32
7.11 Power-Supply Considerations ................................................................................................................... 32
7.12 Initialization................................................................................................................................................ 32
8
REGISTER DESCRIPTIONS.............................................................................................................................. 33
8.1
8.2
Status Bits ................................................................................................................................................. 33
Configuration Fields................................................................................................................................... 33
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Preliminary. Subject to Change Without Notice.
8.3
8.4
9
9.1
9.2
9.3
9.4
DS3106
Multi-Register Fields.................................................................................................................................. 33
Register Definitions ................................................................................................................................... 34
JTAG Description ...................................................................................................................................... 64
JTAG TAP Controller State Machine Description ..................................................................................... 64
JTAG Instruction Register and Instructions............................................................................................... 66
JTAG Test Registers ................................................................................................................................. 67
JTAG TEST ACCESS PORT AND BOUNDARY SCAN..................................................................................... 64
10 ELECTRICAL CHARACTERISTICS ................................................................................................................... 68
10.1 DC Characteristics..................................................................................................................................... 68
10.2 Input Clock Timing..................................................................................................................................... 71
10.3 Output Clock Timing .................................................................................................................................. 71
10.4 SPI Interface Timing .................................................................................................................................. 72
10.5 JTAG Interface Timing............................................................................................................................... 73
10.6 Reset Pin Timing ....................................................................................................................................... 74
11 PIN ASSIGNMENTS ........................................................................................................................................... 75
12 MECHANICAL INFORMATION .......................................................................................................................... 77
13 ACRONYMS AND ABBREVIATIONS................................................................................................................. 79
14 DATA SHEET REVISION HISTORY .................................................................................................................. 80
LIST OF FIGURES
Figure 2-1. Typical Application Example ..................................................................................................................... 6
Figure 3-1. Functional Block Diagram ......................................................................................................................... 6
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 16
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 18
Figure 7-3. FSYNC 8 kHz Options............................................................................................................................. 29
Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 31
Figure 7-5. SPI Bus Transactions.............................................................................................................................. 31
Figure 9-1. JTAG Block Diagram............................................................................................................................... 64
Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 66
Figure 10-1. Recommended Termination for LVDS Output Pins .............................................................................. 70
Figure 10-2 Recommended Termination for LVPECL Level-Compatible Output Pins.............................................. 70
Figure 10-3. SPI Interface Timing Diagram ............................................................................................................... 72
Figure 10-4. JTAG Timing Diagram........................................................................................................................... 73
Figure 10-5. Reset Pin Timing Diagram .................................................................................................................... 74
Figure 11-1. Pin Assignment Diagram....................................................................................................................... 76
Figure 12-1. LQFP Mechanical Dimensions.............................................................................................................. 77
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Preliminary. Subject to Change Without Notice.
DS3106
LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 5
Table 6-1. Input Clock Pin Descriptions ...................................................................................................................... 9
Table 6-2. Output Clock Pin Descriptions.................................................................................................................... 9
Table 6-3. Global Pin Descriptions .............................................................................................................................. 9
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 10
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 11
Table 6-6. Power Supply Pin Descriptions ................................................................................................................ 11
Table 7-1. Input Clock Capabilities ............................................................................................................................ 13
Table 7-2. Input Clock Default Frequency Configuration........................................................................................... 13
Table 7-3. Locking Frequency Modes ....................................................................................................................... 13
Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 20
Table 7-5. Output Clock Capabilities ......................................................................................................................... 22
Table 7-6. Digital1 Frequencies................................................................................................................................. 23
Table 7-7. Digital2 Frequencies................................................................................................................................. 24
Table 7-8. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 24
Table 7-9. T0 APLL Frequency Configuration ........................................................................................................... 24
Table 7-10. T0 APLL2 Frequency Configuration ....................................................................................................... 24
Table 7-11. T4 APLL Frequency Configuration ......................................................................................................... 25
Table 7-12. OC3 and OC6 Output Frequency Selection ........................................................................................... 25
Table 7-13. Possible Frequencies for Programmable Outputs ................................................................................. 26
Table 7-14 T0CR1.T0FREQ Default Settings ........................................................................................................... 28
Table 7-15 T4CR1.T4FREQ Default Settings ........................................................................................................... 28
Table 7-16 OC6 Default Frequency Configuration .................................................................................................... 28
Table 7-17 OC3 Default Frequency Configuration .................................................................................................... 28
Table 8-1. Register Map ............................................................................................................................................ 34
Table 9-1. JTAG Instruction Codes ........................................................................................................................... 66
Table 9-2. JTAG ID Code .......................................................................................................................................... 67
Table 10-1. Recommended DC Operating Conditions .............................................................................................. 68
Table 10-2. DC Characteristics.................................................................................................................................. 68
Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 69
Table 10-4. LVDS Output Pins .................................................................................................................................. 69
Table 10-5. LVPECL Level-Compatible Output Pins................................................................................................. 69
Table 10-6. Input Clock Timing.................................................................................................................................. 71
Table 10-7. Input Clock to Output Clock Delay ......................................................................................................... 71
Table 10-8. Output Clock Phase Alignment, Frame Sync Alignment Mode.............................................................. 71
Table 10-9. SPI Interface Timing ............................................................................................................................... 72
Table 10-10. JTAG Interface Timing.......................................................................................................................... 73
Table 10-11. Reset Pin Timing .................................................................................................................................. 74
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................... 75
Table 12-1. LQFP Thermal Properties, Natural Convection...................................................................................... 78
Table 12-2. LQFP Theta-JA (θ
JA
) vs. Airflow ............................................................................................................. 78
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Preliminary. Subject to Change Without Notice.
DS3106
1 STANDARDS COMPLIANCE
Table 1-1. Applicable Telecom Standards
SPECIFICATION
ANSI
T1.101
TIA/EIA-644-A
ETSI
EN 300 417-6-1
EN 300 462-3-1
EN 300 462-5-1
IEEE
IEEE 1149.1
ITU-T
G.783
G.813
G.823
G.824
G.825
G.8261
G.8262
TELCORDIA
GR-253-CORE
GR-1244-CORE
SPECIFICATION TITLE
Synchronization Interface Standard,
1999
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,
2001
Transmission and Multiplexing (TM); Generic Requirements of Transport Functionality of
Equipment; Part 6-1: Synchronization Layer Functions,
v1.1.3 (1999-05)
Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks;
Part 3-1: The Control of Jitter and Wander within Synchronization Networks,
v1.1.1 (1998-05)
Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks;
Part 5-1: Timing Characteristics of Slave Clocks Suitable for Operation in Synchronous Digital
Hierarchy (SDH) Equipment,
v1.1.1 (1998-05)
Standard Test Access Port and Boundary-Scan Architecture,
1990
ITU G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional
Blocks
(10/2000 plus Amendment 1 06/2002 and Corrigendum 2 03/2003)
Timing characteristics of SDH equipment slave clocks (SEC)
(03/2003)
The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps
Hierarchy
(03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps
Hierarchy
(03/2000)
The Control of Jitter and Wander within Digital Networks which are Based on the
Synchronous Digital Hierarchy (SDH)
(03/2000)
Timing and Synchronization Aspects in Packet Networks
(05/2006)
Timing characteristics of Synchronous Ethernet Equipment slave clock (EEC)
(06/2007,
pre-published)
SONET Transport Systems: Common Generic Criteria,
Issue 3, September 2000
Clocks for the Synchronized Network: Common Generic Criteria,
Issue 2, December 2000
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