EBE21UE8ACWB-8G-E datasheet, PDF

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EBE21UE8ACWB-8G-E: DescriptionDDR DRAM Module, 256MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size244KB，29 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en; Environmental Compliance

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EBE21UE8ACWB-8G-E Overview

DDR DRAM Module, 256MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240

EBE21UE8ACWB-8G-E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ELPIDA
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH; WD-MAX; SEATED HGT-NOM
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM MODULE
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	240
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX8
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	30 mm
self refresh	YES
Maximum standby current	0.16 A
Maximum slew rate	3.04 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm
Base Number Matches	1

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DATA SHEET

2GB Unbuffered DDR2 SDRAM DIMM

EBE21UE8ACWB (256M words

64 bits, 2 Ranks)

Specifications

•

Density: 2GB

•

Organization



256M words

64 bits, 2 ranks

•

Mounting 16 pieces of 1G bits DDR2 SDRAM sealed

in FBGA

•

Package: 240-pin socket type dual in line memory

module (DIMM)



PCB height: 30.0mm



Lead pitch: 1.0mm



Lead-free (RoHS compliant)

•

Power supply: VDD

1.8V

0.1V

•

Data rate: 800Mbps/667Mbps (max.)

•

Eight internal banks for concurrent operation

(components)

•

Interface: SSTL_18

•

Burst lengths (BL): 4, 8

•

/CAS Latency (CL): 3, 4, 5, 6

•

Precharge: auto precharge option for each burst

access

•

Refresh: auto-refresh, self-refresh

•

Refresh cycles: 8192 cycles/64ms



Average refresh period

7.8µs at 0°C

≤

≤ +85°C

3.9µs at

+85°C <

≤ +95°C

•

Operating case temperature range



TC = 0°C to +95°C

Features

•

Double-data-rate architecture; two data transfers per

clock cycle

•

The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

•

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

•

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Posted /CAS by programmable additive latency for

better command and data bus efficiency

•

Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

•

/DQS can be disabled for single-ended Data Strobe

operation

Document No. E1399E10 (Ver. 1.0)

Date Published October 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2008

EBE21UE8ACWB-8G-E Related Products

	EBE21UE8ACWB-8G-E	EBE21UE8ACWB-8E-E
Description	DDR DRAM Module, 256MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX8, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240
Is it Rohs certified?	conform to	conform to
Maker	ELPIDA	ELPIDA
Parts packaging code	DIMM	DIMM
package instruction	DIMM, DIMM240,40	DIMM, DIMM240,40
Contacts	240	240
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.4 ns	0.4 ns
Other features	AUTO/SELF REFRESH; WD-MAX; SEATED HGT-NOM	AUTO/SELF REFRESH; WD-MAX; SEATED HGT-NOM
Maximum clock frequency (fCLK)	400 MHz	400 MHz
I/O type	COMMON	COMMON
JESD-30 code	R-XDMA-N240	R-XDMA-N240
length	133.35 mm	133.35 mm
memory density	2147483648 bit	2147483648 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE
memory width	8	8
Number of functions	1	1
Number of ports	1	1
Number of terminals	240	240
word count	268435456 words	268435456 words
character code	256000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
organize	256MX8	256MX8
Output characteristics	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM
Encapsulate equivalent code	DIMM240,40	DIMM240,40
Package shape	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified
refresh cycle	8192	8192
Maximum seat height	30 mm	30 mm
self refresh	YES	YES
Maximum standby current	0.16 A	0.16 A
Maximum slew rate	3.04 mA	3.04 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	4 mm	4 mm
Base Number Matches	1	1

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