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M2U51264DS88B1G-6K

Description
DDR DRAM Module, 64MX64, CMOS, DIMM-184
Categorystorage    storage   
File Size349KB,17 Pages
ManufacturerNanya
Websitehttp://www.nanya.com/cn
Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.
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M2U51264DS88B1G-6K Overview

DDR DRAM Module, 64MX64, CMOS, DIMM-184

M2U51264DS88B1G-6K Parametric

Parameter NameAttribute value
Parts packaging codeDIMM
package instructionDIMM,
Contacts184
Reach Compliance Codecompliant
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N184
memory density4294967296 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals184
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Base Number Matches1

M2U51264DS88B1G-6K Preview

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M2U1G64DS8HB1G / M2U51264DS88B1G / M2U25664DSH4B1G
M2Y1G64DS8HB1G / M2Y51264DS88B1G / M2Y25664DSH4B1G (Green)
1GB, 512MB and 256MB
PC3200 and PC2700
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
Based on DDR400/333 512M bit Die B device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 110nm 512M bit die B device
• Performance:
Speed Sort
DIMM
f
CK
t
CK
Latency
PC2700 PC3200
6K
5T
Unit
2.5
166
6
333
3
200
5
400
MHz
ns
MHz
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
Latency: 2, 2.5 (6K); 2.5, 3 (5T)
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts on module PCB
Clock Frequency
Clock Cycle
f
DQ
DQ Burst Frequency
• Intended for 200 and 166 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= V
DDQ
= 2.5V ± 0.2V (6K); V
DD
= V
DDQ
= 2.6V ± 0.1V (5T)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
Description
M2U1G64DS8HB1G and M2Y1G64DS8HB1G are unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM) and are organized as two ranks of 128Mbx64 high-speed memory array using sixteen 64Mx8 DDR SDRAMs TSOP
packages. M2U51264DS88B1G and M2Y51264DS88B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are organized as a
single rank of 64Mbx64 high-speed memory array using eight 64Mx8 DDR SDRAMs TSOP packages. M2U25664DSH4B1G and
M2Y25664DSH4B1G are unbuffered 200-Pin DDR Synchronous DRAM UDIMM and are organized as a single rank of 32Mbx64 high-speed
memory array using four 32Mx16 DDR SDRAMs TSOP packages.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device
latency and burst /length/operation type must be
programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 1.2
June 2, 2006
1
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