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PBL 386 21/2
Subscriber Line
Interface Circuit
Description
The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in DAML, FITL and other telecommunications equipment. The PBL
386 21/2 has been optimized for low total line interface cost and a high degree of
flexibility in different applications.
The PBL 386 21/2 has constant current feed, programmable to max. 30 mA.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 21/2 is compatible with loop start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
the two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
Key Features
• 24-pin SSOP package
• High and low battery with automatic
switching
• 60 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• 44V open loop voltage @ -48V battery
feed
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Polarity reversal
• Integrated Ring Relay driver
• Ground key detector
• Programmable signal headroom
Ring Relay
Driver
RRLY
• -40
°C
to +85
°C
ambient temperature
range
DT
DR
TIPX
RINGX
HP
Ring Trip
Comparator
Input
Decoder
and
Control
C1
C2
C3
DET
Ground Key
Detector
VCC
VBAT
Off-hook
Detector
PLD
REF
VTX
P
VBAT2
21/2
386
PBL
AGND
BGND
VF Signal
Transmission
RSN
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
Figure 1. Block diagram.
1
38 PB
6 L
21
/2
B
L
38
LP
6
21
/2
Two-wire
Interface
Line Feed
Controller
and
Longitudinal
Signal
Suppression
POV
PSG
PLC
PBL 386 21/2
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
Power supply,
-40
°C ≤
T
Amb
≤
+85
°C
V
CC
with respect to A/BGND
V
Bat2
with respect to A/BGND
V
Bat
with respect to A/BGND, continuous
V
Bat
with respect to A/BGND, 10 ms
Power dissipation
Continuous power dissipation at T
Amb
≤
+85
°C
Ground
Voltage between AGND and BGND
Relay Driver
Ring relay supply voltage
Ring trip comparator
Input voltage
Input current
Digital inputs, outputs
(C1, C2, C3, DET)
Input voltage
Output voltage
TIPX and RINGX terminals,
-40°C < T
Amb
< +85°C, V
Bat
= -50V
Maximum supplied TIPX or RINGX current
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, t
Rep
> 10 s, Note 2
TIPX or RINGX, pulse < 1
µs,
t
Rep
> 10 s, Note 2
TIPX or RINGX, pulse < 250 ns, t
Rep
> 10 s, Notes 2 & 3
T
Stg
T
Amb
T
J
V
CC
V
Bat2
V
Bat
V
Bat
P
D
V
G
-55
-40
-40
-0.4
V
Bat
-75
-80
+150
+110
+140
6.5
0.4
0.4
0.4
1.5
°C
°C
°C
V
V
V
V
W
V
-0,3
0,3
BGND+14 V
V
DT
, V
DR
I
DT
, I
DR
V
ID
V
OD
V
Bat
-5
-0.4
-0.4
AGND
5
V
CC
V
CC
+100
2
5
10
15
V
mA
V
V
I
TIPX
, I
RINGX
-100
V
TA
, V
RA
-80
V
TA
, V
RA
V
TA
, V
RA
V
TA
, V
RA
V
Bat
-10
V
Bat
-25
V
Bat
-35
mA
V
V
V
V
Recommended Operating Condition
Parameter
Symbol
Min
Max
Unit
Ambient temperature
V
CC
with respect to AGND
V
Bat
with respect to AGND
AGND with respect to BGND
T
Amb
V
CC
V
Bat
V
G
-40
4.75
-58
-100
+85
5.25
-8
100
°C
V
V
mV
Notes
1.
2.
3.
The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.
With the diodes D
VB
and D
VB2
included, see figure 12.
R
F1
and R
F2
≥
20
Ω
is also required. Pulse is applied to TIP and RING outside R
F1
and R
F2
.
2
PBL 386 21/2
Electrical Characteristics
-40
°C ≤
T
Amb
≤
+85
°C,
PTG = open (see pin description), V
CC
= +5V
±5
%, V
Bat
= -58V to -40V, V
Bat2
= -17V, R
LC
=38.3 kΩ,
I
L
= 22 mA. R
L
= 600
Ω,
R
F1
= R
F2
= R
P1
= R
P2
=0, R
Ref
= 49.9 kΩ, C
HP
= 47 nF, C
LP
=0.15
µF,
R
T
= 120 kΩ, R
SG
= 0 kΩ, R
RX
= 60 kΩ,
R
R
= 52.3 kΩ R
OV
=
∞
unless otherwise specified. Current definition: current is positive if flowing into a pin.
Parameter
Ref
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overload level, V
TRO
On-Hook, I
Ldc
< 5mA
Input impedance, Z
TR
Longitudinal impedance, Z
LOT
, Z
LOR
Longitudinal current limit, I
LOT
, I
LOR
Longitudinal to metallic balance, B
LM
2
Active state
1% THD
Note 1, R
OV
=
∞
Note 2
0 < f < 100 Hz
active state
1.0
1.0
Z
T
/200
20
10
35
V
Peak
V
Peak
Ω/wire
mA
rms
/wire
dB
dB
dB
75
70
68
75
70
68
50
dB
dB
dB
dB
dB
dB
dB
IEEE standard 455-1985, Z
TRX
=736Ω
0.2 kHz < f < 1.0 kHz
53
1.0 kHz < f < 3.4 kHz
53
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
3
0.2 kHz < f < 1.0 kHz
53
1.0 kHz < f < 3.4 kHz
53
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
3
0.2 kHz < f < 1.0 kHz
53
1.0 kHz < f < 3.4 kHz
53
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
4
0.2 kHz < f < 3.4 kHz
40
Longitudinal to metallic balance, B
LME
B
LME
=20 • Log E
Lo
V
TR
Longitudinal to four-wire balance, B
LFE
B
LFE
= 20 • Log E
Lo
V
TX
Metallic to longitudinal balance, B
MLE
V
B
MLE
= 20 • Log
TR
; E
RX
= 0
V
Lo
C
TIPX
VTX
Figure 2. Overload level, V
TRO
, two-wire
port
1
<< R
L
, R
L
= 600
Ω
ωC
R
T
= 120 kΩ, R
RX
= 60 kΩ
R
L
V
TRO
I
LDC
PBL 386 21/2
RINGX
RSN
R
T
E
RX
R
RX
Figure 3. Longitudinal to metallic (B
LME
)
and Longitudinal to four-wire (B
LFE
)
balance
1
<< 150
Ω,
R
LR
=R
LT
=R
L
/2=300Ω
ωC
R
T
= 120 kΩ, R
RX
= 60 kΩ
TIPX
E
Lo
C
R
LT
V
TR
R
LR
RINGX
VTX
PBL 386 21/2
RSN
R
T
V
TX
R
RX
3
PBL 386 21/2
Parameter
Ref
fig
Conditions
Min
Typ
Max
Unit
Four-wire to longitudinal balance, B
FLE
4
0.2 kHz < f < 4.0 kHz
E
B
FLE
= 20 • Log
RX
V
Lo
r = 20 • Log
|Z
TR
+ Z
L
|
|Z
TR
- Z
L
|
40
50
dB
Two-wire return loss, r
TIPX idle voltage, V
Ti
RINGX idle voltage, V
Ri
V
TR
Four-wire transmit port
(VTX)
Overload level, V
TXO
On-hook, I
L
< 5mA
Output offset voltage
∆V
TX
Output impedance, z
TX
Four-wire receive port
(RSN)
Receive summing node (RSN) DC voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (I
RSN
) to metallic loop current (I
L
)
gain,α
RSN
Frequency response
Two-wire to four-wire, g
2-4
6
5
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active, I
L
= 0 mA
active, I
L
= 0 mA
active, I
L
= 0 mA
Load impedance > 20 kΩ,
1% THD, Note 4
27
20
35
22
- 1.1
V
Bat
+2.5
V
Bat
+3.6
dB
dB
V
V
V
V
Peak
V
Peak
mV
Ω
V
Ω
ratio
1.0
1.0
-100
0.2 kHz < f < 3.4 kHz
I
RSN
= -55
µA
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
1.15
0
15
1.25
8
200
100
50
1.35
20
relative to 0 dBm, 1.0 kHz. E
RX
= 0 V
0.3 kHz < f < 3.4 kHz
f = 8.0 kHz, 12 kHz, 16 kHz
-0.20
-1.0
0.10
0.1
dB
dB
TIPX
C
V
Lo
R
LT
V
TR
R
LR
RINGX
VTX
Figure 4. Metallic to longitudinal and
four-wire to longitudinal balance
R
T
PBL 386 21/2
RSN
E
RX
1
<< 150
Ω,
R
LT
=R
LR
=R
L
/2 =300Ω
ωC
R
T
= 120 kΩ, R
RX
= 60 kΩ
R
RX
C
R
L
I
LDC
E
L
TIPX
VTX
Figure 5. Overload level, V
TXO
, four-wire
transmit port
1
<< R
L
, R
L
= 600
Ω
ωC
R
T
= 120 kΩ, R
RX
= 60 kΩ
R
RX
PBL 386 21/2
RINGX
RSN
R
T
V
TXO
4
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