PCI 9060ES
November 1995
PCI Bus Master Interface Chip for
VERSION 1.0
Adapters and Embedded Systems
________________________________________________________________________________
Features_________________________
General Description _______________
The PCI9060ES provides a compact high performance
PCI bus master interface for adapter boards and
embedded systems. The chip’s local bus may connect
directly to Intel’s 80960 processor chips or to any other
similar local buses.
The PCI9060ES allows the i960® processors and other
intelligent controllers to perform direct bus master
transfers on the PCI bus. The PCI9060ES also enables
the local processor to configure other PCI devices in the
system, an important feature for embedded systems.
The PCI9060ES supports both memory mapped and I/O
mapped accesses to the local bus from the PCI bus.
•
•
•
•
PCI Bus Master and Bus Slave transfers up to 132
megabytes/sec supporting three architectures:
- PCI Direct Master adapter
- PCI Slave adapter
- PCI embedded system
Two bi-directional FIFOs (each 16 Lwords deep) for
zero wait-state burst operation; one for Direct Master
interface and one for Direct Slave interface
Supports both multiplexed and non-multiplexed local
buses, 32 or 16 bit. Connects directly to Intel
i960®Cx, Hx, Jx, Kx and Sx processors
Supports PCI bus accesses as both a PCI bus
Master and Target
Two independent bi-directional FIFOs support zero wait-
•
Local bus can run asynchronously to the PCI clock.
state Direct Slave burst transfers between host and local
•
Four 32 bit mailbox and two 8 bit doorbell registers
memory and Direct Bus Master transfers between a
Local Bus Master and the PCI bus.
•
Supports Little Endian/Big Endian swapping
•
Low power CMOS in 208 Pin Plastic QFP Package
________________________________________________________________________________
Figure 1. Typical PCI 9060ES applications
________________________________________________________________________________
©
PLX Technology, Inc., 1995
PLX Technology, Inc., 390 Potrero Avenue, Sunnyvale, CA 94086 (408) 774-9060 FAX (408) 774-2169
Products and Company names are trademarks/registered trademarks of their respective holders
TABLE OF CONTENTS
________________________________________________________________________________
TABLE OF CONTENTS
1. SECTION 1 - PCI 9060ES GENERAL DESCRIPTION ................................................................................................ 5
2. SECTION 2 - BUS OPERATION ................................................................................................................................. 7
2.1 PCI BUS CYCLES...................................................................................................................................................... 7
2.1.1 PCI Target Command Codes ............................................................................................................................... 7
2.1.2 PCI Master Command Codes............................................................................................................................... 7
2.1.2.1 Direct Local to PCI Command Codes.............................................................................................................................. 7
2.2 LOCAL BUS CYCLES ................................................................................................................................................ 8
2.2.1 Local Bus Slave................................................................................................................................................... 8
2.2.2 Local Bus Master ................................................................................................................................................. 8
2.2.2.1 Ready/Wait State Control ............................................................................................................................................... 8
2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM “Burst Terminate” mode) .................................................................... 8
2.2.2.3 Recovery States ............................................................................................................................................................ 8
2.2.2.4 Local Bus Read Accesses............................................................................................................................................... 9
2.2.2.5 Local Bus Write Accesses............................................................................................................................................... 9
2.2.2.6 Direct Slave Write Access to 8 and 16 bit bus ................................................................................................................. 9
2.2.2.7 Local Bus Data Parity ..................................................................................................................................................... 9
2.2.2.8 Local Bus Little/Big Endian ........................................................................................................................................... 10
3. SECTION 3 - FUNCTIONAL DESCRIPTION............................................................................................................. 11
3.1 PCI 9060ES I
NITIALIZATION
........................................................................................................................................ 11
3.2 RESET..................................................................................................................................................................... 11
3.2.1 PCI Bus Input RST#........................................................................................................................................... 11
3.2.2 Local Bus Input LRESETi#................................................................................................................................. 11
3.2.3 Local Bus Output LRESETo#............................................................................................................................. 11
3.2.4 Software Reset .................................................................................................................................................. 11
3.3 EEPROM ................................................................................................................................................................. 11
3.3.1 LONG EEPROM LOAD ..................................................................................................................................... 12
3.3.2 SHORT EEPROM LOAD ................................................................................................................................... 13
3.4 I
NTERNAL
R
EGISTER
A
CCESS
....................................................................................................................................... 13
3.4.1 PCI Bus Access to Internal Registers ................................................................................................................. 14
3.4.2 Local Bus Access to Internal Registers............................................................................................................... 14
3.5 D
IRECT
D
ATA
T
RANSFER
M
ODES
................................................................................................................................. 15
3.5.1 Direct Bus Master Operation (Local Master to PCI Bus Access) ......................................................................... 15
3.5.2 Direct Slave Operation (PCI Master to Local Bus Access)................................................................................. 18
3.5.2.1 PCI to Local Address Mapping...................................................................................................................................... 18
3.5.2.2 Deadlock and BREQo ................................................................................................................................................... 20
3.5.2.3 Direct Slave Lock.......................................................................................................................................................... 21
3.5.3 Arbitration .......................................................................................................................................................... 21
3.5.3.1 Local Latency and Pause Timers. ................................................................................................................................. 21
3.6 BREQ
INPUT
. ............................................................................................................................................................ 21
3.7 D
OORBELL
R
EGISTERS
................................................................................................................................................ 22
3.8 M
AILBOX
R
EGISTERS
.................................................................................................................................................. 22
3.9 I
NTERRUPTS
.............................................................................................................................................................. 22
3.9.1 PCI Interrupts (INTA#) ....................................................................................................................................... 22
3.9.1.1 Doorbell Interrupt.......................................................................................................................................................... 22
3.9.1.2 Local Interrupt Input...................................................................................................................................................... 22
3.9.1.3 Master/Target Abort Interrupt ........................................................................................................................................ 23
3.9.2 Local Interrupts (LINTo#) ................................................................................................................................... 23
3.9.2.1 Doorbell Interrupt.......................................................................................................................................................... 23
3.9.2.2 Built In Self Test Interrupt (BIST) .................................................................................................................................. 23
3.9.3 PCI SERR# (PCI NMI) ...................................................................................................................................... 23
3.9.4 Local LSERR# (Local NMI) .............................................................................................................................. 24
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Page - 2 -
Version 1.0
Section C
PCI9060ES
TABLE OF CONTENTS
________________________________________________________________________________
4. SECTION 4 - REGISTERS ....................................................................................................................................... 25
4.1 R
EGISTER
A
DDRESS
M
APPING
..................................................................................................................................... 25
4.2 PCI C
ONFIGURATION
R
EGISTERS
................................................................................................................................. 27
4.2.1 PCI Configuration ID Register (Offset 00h) ........................................................................................................ 27
4.2.2 PCI Command Register (Offset 04h).................................................................................................................. 27
4.2.3 PCI Status Register (Offset 06h)........................................................................................................................ 28
4.2.4 PCI Revision ID Register (Offset 08h)................................................................................................................ 28
4.2.5 PCI Class Code Register (Offset 09 - 0Bh) ........................................................................................................ 29
4.2.6 PCI Cache Line Size Register (Offset 0Ch)........................................................................................................ 29
4.2.7 PCI Latency Timer Register (Offset 0Dh)........................................................................................................... 29
4.2.8 PCI Header Type Register (Offset 0Eh) ............................................................................................................. 29
4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh)...................................................................................... 30
4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h).......................................... 30
4.2.11 PCI Base Address Register for I/O Access to Runtime Registers(Offset 14h)................................................... 31
4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h)................................... 31
4.2.13 PCI Base Address Register (Offset 1Ch).......................................................................................................... 31
4.2.14 PCI Base Address Register (Offset 20h) .......................................................................................................... 31
4.2.15 PCI Base Address Register (Offset 24h) .......................................................................................................... 32
4.2.16 PCI Base Address Register (Offset 28h) .......................................................................................................... 32
4.2.17 PCI Base Address Register (Offset 2Ch).......................................................................................................... 32
4.2.18 PCI Expansion ROM Base Register (Offset 30h).............................................................................................. 32
4.2.19 PCI Interrupt Line Register (Offset 3Ch)........................................................................................................... 32
4.2.20 PCI Interrupt Pin Register (Offset 3Dh) ............................................................................................................ 33
4.2.21 PCI Min_Gnt Register (Offset 3Eh) .................................................................................................................. 33
4.2.22 PCI Max_Lat Register (Offset 3Fh) .................................................................................................................. 33
4.3 L
OCAL
C
ONFIGURATION
R
EGISTERS
............................................................................................................................. 34
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ............................................ 34
4.3.2 Local Address Space 0 Local Base Address (Re-map) Register for PCI to Local Bus (PCI 04h) (LOC 84h)........ 34
4.3.3 Local Arbitration Register (PCI 08h) (LOC 88h).................................................................................................. 35
4.3.4 Big/Little Endian Descriptor Register (PCI 0ch) (LOC 8ch) ................................................................................. 35
4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)............................................. 36
4.3.6 Local Expansion ROM Local Base Address (Re-map) register for PCI to Local Bus and BREQo Control (PCI
14h) (LOC 94h)........................................................................................................................................................... 36
4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h) ...................................... 37
4.3.8 Local Range register for Direct Master to PCI (PCI 1Ch) (LOC 9Ch) .................................................................. 38
4.3.9 Local Bus Base Address register for Direct Master to PCI Memory (PCI 20h) (LOC A0h).................................. 38
4.3.10 Local Base Address for Direct Master to PCI IO/CFG Register (PCI 24h) (LOC A4h) ....................................... 38
4.3.11 PCI Base Address (Re-map) register for Direct Master to PCI (PCI 28h) (LOC A8h) ....................................... 39
4.3.12 PCI Configuration Address Register for Direct Master to PCI IO/CFG (PCI 2Ch) (LOC ACh) ........................... 39
4.4 S
HARED
R
UNTIME
R
EGISTERS
..................................................................................................................................... 40
4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h) ........................................................................................................... 40
4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h) ........................................................................................................... 40
4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h) ........................................................................................................... 40
4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh) .......................................................................................................... 40
4.4.5 PCI to Local Doorbell Register (PCI 60h) (LOC E0h) ......................................................................................... 41
4.4.6 Local to PCI Doorbell Register (PCI 64h) (LOC E4h) ......................................................................................... 41
4.4.7 Interrupt Control/Status (PCI 68h) (LOC E8h) .................................................................................................... 42
4.4.8 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh)............ 43
4.4.9 PCI Configuration ID Register (PCI 70h) (LOC F0h).......................................................................................... 43
5. SECTION 5 - PIN DESCRIPTION.............................................................................................................................. 44
5.1 P
IN
S
UMMARY
............................................................................................................................................................ 44
6. SECTION 6 - ELECTRICAL AND TIMING SPECIFICATIONS .................................................................................. 56
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Version 1.0
Section C
PCI9060ES
TABLE OF CONTENTS
________________________________________________________________________________
7. SECTION 7 - PACKAGE MECHANICAL DIMENSIONS AND.................................................................................... 59
7.1 P
ACKAGE
M
ECHANICAL
D
IMENSIONS
............................................................................................................................. 59
7.2 T
YPICAL
A
DAPTER
/E
MBEDDED
S
YSTEM
......................................................................................................................... 60
7.3 C
X
MODE PIN OUT.................................................................................................................................................. 61
7.4 J
X
MODE PIN OUT .................................................................................................................................................. 62
7.5 S
X
MODE PIN OUT.................................................................................................................................................. 63
8. SECTION 8- TIMING DIAGRAMS ............................................................................................................................. 64
8.1 L
IST OF
T
IMING
D
IAGRAMS
........................................................................................................................................... 64
REVISION HISTORY
Date
12/31/94
04/14/95
Revision
0.1
0.2
Comment
Initial draft from PCI9060 Rev 0.9.
1. DEN# is an I/O pin in JX mode
2. Updated timing diagrams
3. Improved Tvalid max specifications
4. Incorporated Big Endian specifications
Correction of typographical errors,
Clarification of specifications,
and Updated Timing Diagrams.
All FIFOs are 16 Lwords deep,
Added additional Device and Vendor ID register(LOC F0h)(PCI 70h),
Updated the AC Characterization data,
Added three more timing diagrams (for WAITi# signal), Timing Diagram 30, 31, and 32,
Added Single Read Access Mode(see bit #15 of Local Bus Region Descriptor (LOC 98h)),
and Added the Write and Invalidate mode with 4 bit programmable Almost Full Flag(see LOC A8h).
Correction of typographical errors.
09/01/95
11/01/95
0.3
0.9
1/5/96
1.0
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Page - 4 -
Version 1.0
Section C
PCI9060ES
SECTION 1
GENERAL DESCRIPTION
________________________________________________________________________________
1. SECTION 1 - PCI 9060ES GENERAL DESCRIPTION
The PCI9060ES is a PCI bus master interface chip that connects a PCI host bus to three local bus types, selected
through mode pins. Each local bus configuration matches the protocol of an Intel 80960 processor, but the PCI 9060ES
may be connected to any local bus with a similar design.
Mode
Description
80960 processor
Cx
32 bit address / 32 bit data, non-multiplexed
Cx, Hx
Jx
32 bit address / 32 bit data, multiplexed
Jx, Kx
Sx
32 bit address / 16 bit data, multiplexed
Sx
The PCI 9060ES is a pin and software-compatible subset of the PCI 9060. Therefore, equipment designed using the PCI
9060 may convert to the lower cost PCI 9060ES with no changes to the hardware design or software. It is identical to the
PCI 9060 except it does not include a DMA controller and it has a smaller mailbox and doorbell register function. The
PCI 9060ES also has deeper slave FIFOs than the PCI 9060 and has a few additional features such as LOCK support,
additional wait-state generation capability, a buffered PCI clock, programmable prefetch size, Big/Small Endian, and PCI
Specification 2.1 compliance.
Differences Between PCI 9060 and PCI 9060ES
Feature
PCI 9060 (Rev. 3)
1. Two Channel Chaining DMA controller
Yes
2.Mailbox Registers
Eight 32 bit
3.Doorbell Registers
Two 32 bit
4.Bi-directional slave and master FIFO depth
8/4 Lwords (32/16bytes)
5.LLOCKo# pin for lock cycles
No
6.WAITi# pin for wait state generation
No
7.BPCLKO pin; buffered PCI clock
No
8.
DREQ,DACK pins for demand mode DMA support
Yes
9. Big/Little Endian Conversion
No
10. PCI Spec 2.1 Deferred Reads
No
11. Programmable Prefetch Counter
No
12. Write & invalidate cycle
No
13. Additional Device and Vender ID register.
No
14. Register addresses
Identical except PCI
9060ES has no DMA
registers
15. Pinout
Identical (except 5,6,7,8)
16. All other features
Identical
PCI 9060ES
No
Four 32 bit
Two 8 bit
16 Lwords (64 bytes)
Yes
Yes
Yes
No
Yes. See Table 26.
Yes. See Table 25.
Yes. See Table 29.
Yes. See page 15 for more details.
Yes. See (LOC F0h)
Identical, except PCI 9060ES has no
DMA registers, and Tables 25, 26, and
43 were added.
Identical (except 5,6,7,8)
Identical
The three most common applications for the chip are direct master adapter, direct slave adapter and embedded system.
Figure 1 shows simplified examples of these design alternatives. There are many other possible variations and
combinations.
Direct Master Adapter:
In the direct master adapter application, the PCI 9060ES typically connects an intelligent I/O
controller (e.g. LAN, disk control, graphics) or processor to the PCI bus. It is called “direct” master because the data
passes directly between the controller or processor and the PCI bus, without an intermediate stop in local adapter
memory. Typically, the adapter’s controller or processor has an Intel mode system interface, meaning its protocol is
close to the X86 or 80960 protocol. The controller or processor performs a local bus master cycle and the PCI 9060ES
automatically translates this into a PCI bus master cycle. FIFOs in the PCI 9060ES allow the PCI bus and the adapter
local bus to operate asynchronously and also enable zero wait-state burst transfers on the PCI bus.
A Direct Master adapter may also operate as a slave. Typically, the slave mode is used by the host to configure or
initialize the controller or processor’s registers. Data transfer is usually performed in the direct master mode.
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Version 1.0
Section C
PCI9060ES
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