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CD-700-LAC-HFB-24.960

Description
Phase Locked Loop, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size115KB,2 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Environmental Compliance  
Download Datasheet Parametric View All

CD-700-LAC-HFB-24.960 Overview

Phase Locked Loop, CQCC16, HERMETIC SEALED, CERAMIC, SMD-16

CD-700-LAC-HFB-24.960 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSOIC
package instructionQCCN,
Contacts16
Reach Compliance Codecompliant
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeR-CQCC-N16
JESD-609 codee4
length7.49 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeRECTANGULAR
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height2.13 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceGOLD OVER NICKEL
Terminal formNO LEAD
Terminal pitch1.02 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width5.08 mm
Base Number Matches1
Clock and Data Recovery Products
CD-700
Description:
Vectron’s CD-700 is a user-configurable crystal based
PLL integrated circuit. It includes a digital phase
detector, op-amp, VCXO and additional integrated
functions for use in digital synchronization
applications
Performance Characteristics
Parameter
Output Frequency: (ordering option)
Out 1, 5V option
Out 1, 3.3V option
Supply Voltage1:
+5.0
+3.3
Supply Current:
Output Logic Levels:
Output Logic High
Output Logic Low
Output Transition Times:
Rise Time2
Fall Time2
Input Logic Levels:
Input Logic High2
Input Logic Low2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle2
Out 1
Out 2
RCLK
Absolute Pull Range
(ordering option)
over operating temp, aging, p.s. variations
Test Conditions for APR (+5V option)
Test Conditions for APR (+3.3V option)
Transfer Function
Phase Detector Gain
+5.0V option
+3.3V option
Operating temperature (ordering option)
Control Voltage Leakage Current
I
VCXO
SYM1
SYM2
RCLK
APR
V
IH
V
OL
V
DD
Features:
·
5 x 7.5mm, smallest VCXO PLL available
·
Output Frequencies to 65.536 MHz
·
5 or 3.3 Vdc operation
·
Tri-state Output
·
Loss of Signal Alarm
·
VCXO with CMOS outputs
·
0/70 or -40/85°C temperature range
·
Hermetically sealed ceramic SMD package
Symbol
Min.
12.000
12.000
4.5
3.0
I
DD
V
OH
V
OL
tR
tF
2.0
0.5
±75
±75
40
45
40
±50, ±80, ±100
60
55
60
2.5
0.5
5
5
5.0
3.3
Typical
Max
65.536
51.840
5.5
3.3
63
Unit
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
ppm
ppm
%
%
%
ppm
V
C
V
C
0.5
0.3
Positive
0.53
0.35
0/70 or -40/85
4.5
3.0
V
V
rad/V
rad/V
o
C
+1
uA
1. A 0.01 uF capacitor should be located as close to the supply as possible (to ground) and a 0.1 uF is also recommended.
2. Symmetry is defined as (ON TIME/PERIOD) with V
S
= 1.4V for both 5V and 3.3V operation.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
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