CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air, with “direct attach” features. See
Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Test Conditions: V
CC
= 12V, T
J
= 0°C to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
V
CC
SUPPLY CURRENT
Input Bias Supply Current
Input Bias Supply Current
POWER-ON RESET
Rising V
CC
POR Threshold
V
CC
POR Threshold Hysteresis
OSCILLATOR
Switching Frequency
I
VCC_dis
I
VCC_en
V
POR
V
CC
= 12V; disabled
V
CC
= 12V; enabled (but not switching)
6.4
7.0
8.9
10.4
mA
mA
3.8
0.15
4.2
0.48
4.47
0.85
V
V
f
OSC
ISL6341C, ISL6341CC
ISL6341I, ISL6341CI
ISL6341AC, ISL6341BC
ISL6341AI, ISL6341BI
270
240
540
510
300
300
600
600
1.5
330
330
660
660
kHz
kHz
kHz
kHz
V
P-P
Ramp Amplitude (Note 3)
REFERENCE
Reference Voltage Tolerance
ΔV
OSC
V
REF
ISL6341C, ISL6341AC, ISL6341BC,
ISL6341CC
ISL6341I, ISL6341AI, ISL6341BI, ISL6341CI
0.7936
0.7920
0.8000
0.8000
0.8064
0.8080
V
V
ERROR AMPLIFIER
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
GATE DRIVERS
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
Upper Gate Source Impedance
R
UG-SRCh
V
CC
= 12V; I = 50mA
R
UG-SNKh
V
CC
= 12V; I = 50mA
R
LG-SRCh
V
CC
= 12V; I = 50mA
R
LG-SNKh
V
CC
= 12V; I = 50mA
R
UG-SRCl
V
CC
= 5V; I = 50mA
2.1
1.6
1.4
1.0
2.4
Ω
Ω
Ω
Ω
Ω
GAIN
GBWP
SR
96
20
8
dB
MHz
V/µs
4
FN6538.2
December 2, 2008
ISL6341, ISL6341A, ISL6341B, ISL6341C
Electrical Specifications
Test Conditions: V
CC
= 12V, T
J
= 0°C to +85°C, Unless Otherwise Noted. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
1.7
1.5
1.1
MAX
UNITS
Ω
Ω
Ω
PARAMETER
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
OCSET Current Source
Enable Threshold (COMP/EN pin)
VOS Rising Trip (PGOOD OV; +10%)
VOS Rising Trip (PGOOD OV) Hysteresis
VOS Falling Trip (PGOOD UV; -10%)
VOS Falling Trip (PGOOD UV) Hysteresis
VOS Rising Threshold (OV; +25%)
VOS Falling Threshold (UV; -25%)
(Note 5)
VOS Threshold (OV; 50% of V
OUT
)
VOS Bias Current
PGOOD
NOTES:
R
UG-SNKl
V
CC
= 5V; I = 50mA
R
LG-SRCl
R
LG-SNKl
I
OCSET
V
ENABLE
V
CC
= 5V; I = 50mA
V
CC
= 5V; I = 50mA
LGATE/OCSET = 0V
9
0.683
0.868
10
0.700
0.880
16
11
0.717
0.888
µA
V
V
mV
0.708
0.720
16
0.732
V
mV
0.980
0.580
0.380
VOS = 0.25V
I
PGOOD
= 4mA
-1500
0.10
1.000
0.600
0.400
-250
0.18
1.020
0.620
0.410
-100
0.30
V
V
V
nA
V
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
5. The UVP is disabled on the ISL6341C; no trip point is measured.
Functional Pin Description
VCC (Pin 6)
This pin provides the bias supply for the ISL6341x, as well
as the lower MOSFET’s gate. An internal regulator will
supply bias as VCC rises above 5V, but the LGATE/OCSET
will still be sourced by VCC. Connect a well-decoupled 5V to
12V supply to this pin.
connection available. The metal pad under the package
should also be connected to the GND plane for thermal
conductivity, but does not conduct any current.
PHASE (Pin 2)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
FB (Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/EN pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from V
OUT
to FB to GND is used to set the regulation voltage.
UGATE (Pin 3)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
VOS (Pin 9)
This input pin monitors the regulator output for OV and UV
protection, and PGOOD (OV and UV). Connect a resistor
divider from V
OUT
to VOS to GND, with the same ratio as
the FB resistor divider. It is not recommended to share one
divider for both FB and VOS; the response to a fault may not
be as quick or robust. There is a small pull-up bias current
on the pin; if the VOS pin is not connected, the OV protection
would be tripped to protect the load.
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-Channel MOSFET (equal to V
GD
minus
the BOOT diode voltage drop), with respect to PHASE.
COMP/EN (Pin 7)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/EN, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
GND (Pin 5)
This pin represents the signal and power ground for the IC.
This pin is the high current connection, and should be tied to
the ground island/plane through the lowest impedance
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