80V, 500mA, 3-Phase MOSFET Driver
HIP4086, HIP4086A
The HIP4086 and HIP4086A (referred to as the HIP4086/A) are
three phase N-Channel MOSFET drivers. Both parts are
specifically targeted for PWM motor control. These drivers have
flexible input protocol for driving every possible switch
combination. The user can even override the shoot-through
protection for switched reluctance applications.
The HIP4086/A have a wide range of programmable dead times
(0.5µs to 4.5µs) which makes them very suitable for the low
frequencies (up to 100kHz) typically used for motor drives.
The only difference between the HIP4086 and the HIP4086A is
that the HIP4086A has the built-in charge pumps disabled. This
is useful in applications that require very quiet EMI performance
(the charge pumps operate at 10MHz). The advantage of the
HIP4086 is that the built-in charge pumps allow indefinitely long
on times for the high-side drivers.
To insure that the high-side driver boot capacitors are fully
charged prior to turning on, a programmable bootstrap refresh
pulse is activated when VDD is first applied. When active, the
refresh pulse turns on all three of the low-side bridge FETs while
holding off the three high-side bridge FETs to charge the
high-side boot capacitors. After the refresh pulse clears, normal
operation begins.
Another useful feature of the HIP4086/A is the programmable
undervoltage set point. The set point range varies from 6.6V to
8.5V.
Features
• Independently drives 6 N-Channel MOSFETs in three phase
bridge configuration
• Bootstrap supply max voltage up to 95VDC with bias supply
from 7V to 15V
• 1.25A peak turn-off current
• User programmable dead time (0.5µs to 4.5µs)
• Bootstrap and optional charge pump maintain the high-side
driver bias voltage.
• Programmable bootstrap refresh time
• Drives 1000pF load with typical rise time of 20ns and Fall
Time of 10ns
• Programmable undervoltage set point
Applications
• Brushless Motors (BLDC)
• 3-phase AC motors
• Switched reluctance motor drives
• Battery powered vehicles
• Battery powered tools
Related Literature
•
AN9642
“HIP4086 3-Phase Bridge Driver Configurations and
Applications”
VDD
200
VDD
RDEL
CHB
BHB
AHB
V
xHB
- V
xHS
= 10V
OUTPUT CURRENT (µA)
150
AHO
HIP4086/A
BHO
CHO
CHS
BHS
AHS
Speed
Battery
24V...48V
AHI
ALI
Controller
Brake
BHI
BLI
CHI
CLI
100
VSS
ALO
BLO
CLO
50
0
-60
-40
-20
0
20
40
60
80
100 120 140 160
JUNCTION TEMPERATURE (°C)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. CHARGE PUMP OUTPUT CURRENT
February 1, 2013
FN4220.9
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HIP4086, HIP4086A
Block Diagram
(for clarity, only one phase is shown)
If undervoltage is active or if
DIS is asserted, the high and
low-side drivers are turned off.
Drive Enable
Common with
all phases
Adjustable
Turn-on
Delay
10ns
delay
Undervoltage
Detector
Delay Disable
VDD
Charge
Pump*
EN
16
xHB
xHI
5
DIS
10
VDD
20
UVLO
8
RFSH
9
Level
Shifter
*The charge pump is
permanently disabled
in the HIP4086A.
17
xHO
18
xHS
Refresh
Pulse
Common with
all phases
Adjustable
Turn-on
Delay
Common with
all phases
VDD
21
xLO
6
VSS
xLI
4
RDEL
7
2µs Delay
Common with
all phases
100mV
If the voltage on RDEL is less than 100mV, the
turn-on delay timers are disabled and the high and
low-side drivers can be turned on simultaneously .
Truth Table
INPUT
ALI, BLI, CLI
X
X
1
0
0
1
AHI, BHI, CHI
X
X
X
0
1
0
UV
X
1
0
0
0
0
DIS
1
X
0
0
0
0
RDEL
X
X
>100mV
X
X
<100mV
OUTPUT
ALO, BLO, CLO
0
0
1
0
0
1
AHO, BHO, CHO
0
0
0
1
0
1
NOTE: X signifies that input can be either a “1” or “0”.
2
FN4220.9
February 1, 2013
HIP4086, HIP4086A
Pin Configuration
HIP4086, HIP4086A
(PDIP, SOIC)
TOP VIEW
BHB
1
BHI
2
BLI
3
ALI
4
AHI
5
VSS
6
RDEL
7
UVLO
8
RFSH
9
DIS
10
CLI
11
CHI
12
24
BHO
23
BHS
22
BLO
21
ALO
20
VDD
19
CLO
18
AHS
17
AHC
16
AHB
15
CHS
14
CHO
13
CHB
Pin Descriptions
PIN NUMBER
16
1
13
15
23
15
5
2
12
SYMBOL
AHB
BHB
CHB
(xHB)
AHS
BHS
CHS
(xHS)
AHI
BHI
CHI
(xHI)
DESCRIPTION
High-Side Bias Connections. One external bootstrap diode and one capacitor are required for
each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB
pin.
High-Side Source Connections. Connect the sources of the High-Side power MOSFETs to these
pins. The negative side of the bootstrap capacitors are also connected to these pins.
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output
drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI
is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the
low side input of each phase will override the corresponding high side input on that phase -
see “Truth Table” on page 2. If RDEL is tied to ground, dead time is disabled and the outputs
follow the inputs with no shoot-thru protection. DIS (Pin 10) also overrides the high side inputs.
xHI can be driven by signal levels of 0V to 15V (no greater than V
DD
).
Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output
drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the
lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL
(Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by
signal levels of 0V to 15V (no greater than V
DD
).
Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
Delay Time Set point. Connect a resistor from this pin to V
DD
to set timing current that defines
the dead time between drivers - see Figure 17. All drivers turn-off with minimal delay, RDEL
resistor prevents shoot-through by delaying the turn-on of all drivers. When RDEL is tied to V
SS
,
both upper and lowers can be commanded on simultaneously. While not necessary in most
applications, a decoupling capacitor of 0.1µF or smaller may be connected between RDEL and
V
SS
.
Undervoltage Set point. A resistor can be connected between this pin and V
SS
to program the
undervoltage set point - see Figure 18. With this pin not connected, the under voltage disable
is typically 6.6V. When this pin is tied to V
DD
, the under voltage disable is typically 6.2V.
Refresh Pulse Setting. An external capacitor can be connected from this pin to V
SS
to increase
the length of the start up refresh pulse - see Figure 16. If this pin is not connected, the refresh
pulse is typically 1.5µs.
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high
overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can
be driven by signal levels of 0V to 15V (no greater than V
DD
).
4
3
11
ALI
BLI
CLI
(xLI)
V
SS
RDEL
6
7
8
UVLO
9
RFSH
10
DIS
3
FN4220.9
February 1, 2013
HIP4086, HIP4086A
Pin Descriptions
(Continued)
PIN NUMBER
17
24
14
20
21
22
19
NOTE: x = A, B or C.
SYMBOL
AHO
BHO
CHO
(xHO)
V
DD
ALO
BLO
CLO
(xLO)
DESCRIPTION
High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
Positive Supply. Decouple this pin to V
SS
(Pin 6).
Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
Ordering Information
PART NUMBER
(Notes 1, 3)
HIP4086AB
HIP4086ABZ (Note 2)
HIP4086APZ (Note 2)
HIP4086AABZ (Note 2)
NOTES:
1. Add “-T*”, suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
HIP4086, HIP4086A.
For more information on MSL, please see Technical
Brief
TB363.
PART
MARKING
HIP4086AB
HIP4086ABZ
HIP4086APZ
HIP4086AABZ
TEMP RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
CHARGE
PUMP
Yes
Yes
Yes
No
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld PDIP (Pb-free)
24 Ld SOIC (Pb-free)
PACKAGE
PKG.
DWG. #
M24.3
M24.3
E24.3
M24.3
4
FN4220.9
February 1, 2013
HIP4086, HIP4086A
Absolute Maximum Ratings
(Note 7)
Supply Voltage, V
DD
Relative to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Voltage on xHS . . . . . . . . . . . . . . -6V (Transient) to 85V (-40
°
C to +150
°
C)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
xHS
- 0.3V to V
xHS
+V
DD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
- 0.3V to V
DD
+0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
xHS
- 0.3V to V
xHB
+0.3V
Phase slew rate (on xHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
SOIC Package (Notes 4, 6) . . . . . . . . . . . . .
75
22
SOIC Package HIP4086AABZ (Notes 5, 6)
51
22
PDIP* Package (Notes 4, 6) . . . . . . . . . . . .
70
29
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
Maximum Recommended Operating
Conditions
Supply Voltage, V
DD
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . 7V to 15V
Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
6. For
θ
JC
, the “case temp” location is taken at the package top center.
7. Replace x with A, B, or C.
DC Electrical Specifications
V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 20k, R
UV
=
∞
,
Gate Capacitance (C
GATE
) = 1000pF,
unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +150°C.
T
J
= +25°C
PARAMETER
TEST CONDITIONS
xHI = 5V, xLI = 5V (HIP4086)
xHI = 5V, xLI = 5V (HIP4086A)
f = 20kHz, 50% Duty Cycle (HIP4086)
f = 20kHz, 50% Duty Cycle (HIP4086A)
xHI = 0V (HIP4086)
xHI = 0V (HIP4086A)
xHI = V
DD
(HIP4086)
xHI = V
DD
(HIP4086A)
f = 20kHz, 50% Duty Cycle (HIP4086)
f = 20kHz, 50% Duty Cycle (HIP4086A)
V
xHS
= 80V, V
xHB
= 93V
No Load
V
xHS
= 12V, V
xHB
= 22V
R
UV
open
R
UV
open
R
UV
= V
DD
0.6
0.8
0.7
0.8
7
11.5
50
6.2
5.75
5
-
MIN
(Note 9)
2.7
2.3
6.3
3.1
-
TYP
3.4
2.4
8.25
3.6
40
80
0.8
0.9
0.9
0.9
24
12.5
100
7.1
6.6
6.2
-
MAX
(Note 9)
4.2
2.6
10.5
4.1
80
100
1.3
1
1.3
1
45
14
130
8.0
7.5
6.8
1.0
0.5
0.7
-
-
-
10.5
-
6.1
5.6
4.9
-
T
J
= -40°C TO +150°C
MIN
(Note 9)
2.1
2.1
5
2.8
-
MAX
(Note 9)
4.3
2.7
11
4.4
100
200
1.4
1.2
2.0
1.2
50
14.5
140
8.1
7.6
6.9
0.8
UNITS
mA
mA
mA
mA
µA
µA
mA
mA
mA
mA
µA
V
µA
V
V
V
V
SUPPLY CURRENTS
V
DD
Quiescent Current
V
DD
Operating Current
xHB On Quiescent Current
xHB Off Quiescent Current
xHB Operating Current
xHB, xHS Leakage Current
Q
PUMP
Output Voltage
Q
PUMP
Output Current
Charge Pump, HIP4086 only, (Note 8)
UNDERVOLTAGE PROTECTION
V
DD
Rising Undervoltage Threshold
V
DD
Falling Undervoltage Threshold
Minimum Undervoltage Threshold
Low Level Input Voltage
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
5
FN4220.9
February 1, 2013
Power technology
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