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CY37064P44-167AI

Description
EE PLD, 6.5ns, 64-Cell, CMOS, PQFP44, PLASTIC, TQFP-44
CategoryProgrammable logic devices    Programmable logic   
File Size420KB,20 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY37064P44-167AI Overview

EE PLD, 6.5ns, 64-Cell, CMOS, PQFP44, PLASTIC, TQFP-44

CY37064P44-167AI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFP
package instructionPLASTIC, TQFP-44
Contacts44
Reach Compliance Codecompliant
Other featuresYES
maximum clock frequency125 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G44
JESD-609 codee0
JTAG BSTYES
Dedicated input times1
Number of I/O lines32
Number of macro cells64
Number of terminals44
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1 DEDICATED INPUTS, 32 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP44,.47SQ,32
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5,5 V
Programmable logic typeEE PLD
propagation delay6.5 ns
Certification statusNot Qualified
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
6
PRELIMINARY
CY37064
UltraLogic™ 64-Macrocell ISR™ CPLD
Features
• 64 macrocells in four logic blocks
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• Up to 64 I/Os
— plus 5 dedicated inputs including 4 clock inputs
• High speed
— f
MAX
= 167 MHz
— t
PD
= 6.5 ns
— t
S
= 3.5 ns
— t
CO
= 4.5 ns
Product-term clocking
IEEE 1149.1 JTAG boundary scan
Programmable slew rate control on individual I/Os
Low power option on individual logic block basis
5V and 3.3V I/O capability
User-Programmable Bus Hold capabilities on all I/Os
Simple Timing Model
PCI compliant
44–100 pins in TQFP, PLCC, and CLCC packages
Pinout compatible with the CY37064V, CY37032/
37032V, CY37128/37128V, CY7C372i, CY7C373i
Logic Block Diagram (100-pin TQFP)
Clock/
Input
Input
1
4
4
36
I/O
0
−I/O
15
16 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
B
16
36
16 I/Os
I/O
16
−I/O
31
16
36
16
4
PIM
LOGIC
BLOCK
D
LOGIC
BLOCK
C
16 I/Os
I/O
48
−I/O
63
36
16 I/Os
I/O
32
−I/O
47
16
32
TDI
TCLK
TMS
JTAG Tap
Controller
TDO
32
37064-1
Selection Guide
CY37064-200
Maximum Propagation Delay, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Typical Supply Current, I
CC
(mA) in Low Power Mode
6.0
4
4
30
CY37064-167
6.5
4
4
30
CY37064-125
10
5.5
6.5
30
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA95134
408-943-2600
January 6, 1999
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