6
PRELIMINARY
CY37064
UltraLogic™ 64-Macrocell ISR™ CPLD
Features
• 64 macrocells in four logic blocks
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• Up to 64 I/Os
— plus 5 dedicated inputs including 4 clock inputs
• High speed
— f
MAX
= 167 MHz
— t
PD
= 6.5 ns
•
•
•
•
•
•
•
•
•
•
— t
S
= 3.5 ns
— t
CO
= 4.5 ns
Product-term clocking
IEEE 1149.1 JTAG boundary scan
Programmable slew rate control on individual I/Os
Low power option on individual logic block basis
5V and 3.3V I/O capability
User-Programmable Bus Hold capabilities on all I/Os
Simple Timing Model
PCI compliant
44–100 pins in TQFP, PLCC, and CLCC packages
Pinout compatible with the CY37064V, CY37032/
37032V, CY37128/37128V, CY7C372i, CY7C373i
Logic Block Diagram (100-pin TQFP)
Clock/
Input
Input
1
4
4
36
I/O
0
−I/O
15
16 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
B
16
36
16 I/Os
I/O
16
−I/O
31
16
36
16
4
PIM
LOGIC
BLOCK
D
LOGIC
BLOCK
C
16 I/Os
I/O
48
−I/O
63
36
16 I/Os
I/O
32
−I/O
47
16
32
TDI
TCLK
TMS
JTAG Tap
Controller
TDO
32
37064-1
Selection Guide
CY37064-200
Maximum Propagation Delay, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Typical Supply Current, I
CC
(mA) in Low Power Mode
6.0
4
4
30
CY37064-167
6.5
4
4
30
CY37064-125
10
5.5
6.5
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA95134
•
408-943-2600
January 6, 1999
PRELIMINARY
Functional Description
The CY37064 is an In-System Reprogrammable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Like
all members of the Ultra37000 family, the CY37064 is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs
.
# of
Pins
44
84
100
# Buried
Macrocells
32
0
0
# I/O
Macrocells
32
64
64
Package
Types
TQFP PLCC
,
PLCC
TQFP
CY37064
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns max. and in the slow edge rate mode, outputs switch at
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
3.3V or 5V I/O Operation
The CY37064 operates with a 5V supply, and can support 5V
or 3.3V I/O levels. V
CCO
connections provide the capability of
interfacing to either a 5V or 3.3V bus. By connecting the V
CCO
pins to 5V the user insures 5V TTL levels on the outputs. If
V
CCO
is connected to 3.3V the output levels meet 3.3V JEDEC
standard CMOS levels and are 5V tolerant. A nominal timing
delay is incurred on output buffers when V
CCO
is set to 3.3V.
This device requires 5V ISR programming.
In-System Reprogramming
The CY37064 can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The CY37064
can also be programmed on a number of traditional parallel
programmers including Cypress’s
Impulse3
™
programmer
and industry standard third-party programmers. For an over-
view of ISR programming, refer to the Ultra37000 Family data
sheet and for UltraISR cable and software specifications, refer
to InSRkit: ISR Programming data sheet (CY3600i).
User-Programmable Bus Hold
All outputs of the CY37064 can either be configured into bus
hold mode or left floating. When in bus hold mode, the undriv-
en outputs retain their last value with a weak latch. This feature
allows the designer the flexibility of either eliminating or includ-
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os simultaneously.
Design Tools
Development software for the CY37064 is available from
Cypress’s
Warp
™
or third-party bolt-in software packages as
well as a number of third-party development packages. Please
refer to the
Warp
or third-party tool support data sheets for
further information.
For a more detailed description of the architecture and fea-
tures of the CY37064 see the Ultra37000 family data sheet.
Fully Routable with 100% Logic Utilization
The CY37064 is designed with a robust routing architecture
which allows utilization of the entire device with a fixed pinout.
This makes Ultra37000 optimal for implementing on-board de-
sign changes using ISR without changing pinouts.
Simple Timing Model
The CY37064 features a very simple timing model with pre-
dictable delays. Unlike other high-density CPLD architectures,
there are no hidden speed delays such as fanout effects, inter-
connect delays, or expander delays. The timing model allows
for design changes with ISR without causing changes to sys-
tem performance.
Low Power Operation
Each Logic Block of the CY37064 can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
the logic block consumes approximately 50% less power and
slows down by t
LP
.
Output Slew Rate Control
Each output can be configured with either a fast edge rate
(default) for high performance, or a slow edge rate for added
2